BCDMOS evolves to handle broad range of UHV apps

BCDMOS continues to evolve as the preferred process for integrating bipolar (analogue), CMOS (logic) and DMOS (power) functions on a single chip destined for ultra high voltage (UHV) applications. While we have recently witnessed the effectiveness of optimising DR-LDMOS (Double RESURF Laterally Diffused Metal Oxide Semiconductor) transistors to specify breakdown voltages up to 900V for demanding industrial applications, there is now another evolution of this process that enables the implementation of a broader range of product designs that specify breakdown voltages of only up to 750V.

Benefits of non-epi process
By eliminating the epitaxial layer and optimising active components, BCDMOS can serve a broad range of UHV applications such as LED lighting, AC-DC conversion and switched mode power supplies. Capable of operating directly "off line" from a 110/220VAC source, ICs implemented with the non-Epi process can deploy optimised 450V/700V DR-LDMOS transistors that specify low on resistance and a breakdown voltage that exceeds 750V. When used in power switching applications, designers can expect lower conduction and switching losses.

To appreciate just how a non-Epi BCDMOS process can deliver new levels of UHV design flexibility and cost savings, it is instructive to delve into the process itself. Indeed, creating new product designs have come a long way beyond evaluating catalogue ICs.

While there is much to consider in evaluating the latest BCDMOS processes, for the purpose of this article we shall focus on how LDMOS and JFET transistors do the heavy lifting when it comes to handling high voltages. We will also provide an overview of how low voltage functions are being optimised to specify electrical characteristics that make them useful when integrated into UHV system-on-chip designs.

Optimising DR-LDMOS to decrease on-resistance
The DR-LDMOS transistors used in a non-Epi BCDMOS process are very sensitive to the integrated charge of n-type drift of the source corner region. This sensitivity is particularly evident when trying to decrease on-resistance while maintaining a robust breakdown voltage.

The success of the RESURF (Reduced SURface Field) technique requires optimisation of several key parameters such as n-type charge, doping concentrations and device layout geometry. As shown in figure 1b, on-resistance is reduced with an additional P-TOP layer (P-type charge, QP) inside an extended n-type drift region (HVNWELL). The total charge (QN) in the HVNWELL region can be increased twice as much as that in the single RESURF LDMOS (figure 1a) to minimise on-resistance.

Let's now take a look at the NLDMOS cross-section shown in figure 2a where the Double RESURF technique is applied. Here, the additional P-Top layer of opposite conductivity is incorporated inside the extended n-type drift region to reduce on-resistance while maintaining high breakdown voltage. The electrical characteristics charted in figure 2b make this 450/700V transistor ideal for use in power switching devices such as those needed for LED lighting, switched-mode power supplies and data conversion.

Variable voltage JFETs without additional masks
The simplest type of field-effect transistor, the JFET, continues to be an essential workhorse in high-voltage designs. It can be used as an electronically controlled switch or as a voltage-controlled resistance. By applying a reverse bias voltage to the gate terminal, the channel to the drain is "pinched" thereby reducing current flow or stopping it entirely.