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How to avoid PCB engineering change orders

Posted: 13 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Engineering change orders? design for test? moisture sensitivity levels? DFT? PCB?

Engineering change orders (ECOs) raise design costs and result to numerous delays in product development, thus leading to costly extension of time to market. However, most ECOs can be avoided by paying careful attention to seven critical areas where problems frequently occur: component selection, memory, moisture sensitivity levels (MSL), design for test (DFT), cooling methodologies, heat sinks, and coefficient of thermal expansion (CTE).

Component selection
A meticulous review of all a component's specifications is crucial to avoid ECOs. Initially the PCB designer may routinely check out electrical and engineering data as well as end of life and availability. But when a component is in the early stages of market introduction, all the critical specifications may not yet be available on the data sheet. The reliability data currently available may not be extensive or sufficiently detailed when the component has been on the market for only a few months or is available only in small sample quantities. Consequently, there may not be a sufficient amount of reliability and quality assurance data on field failures, for example.

It's important not to accept the spec sheet at face value, but to contact the component vendor to learn as much as possible about a component's characteristics and how these characteristics relate to the design.

An example is the expected maximum current flow or voltage the component will need to handle. If the component is not selected for sufficient current or voltage, the component may burn out. Figure 1 shows a burned capacitor.

Figure 1: Considerable current or voltage flowing through the circuitry due to poor component selection can result in damage like this burned capacitor.

Let's take another example, a land grid array (LGA) packaged device. In addition to electrical and mechanical constraints, you may need to consider the kind of solder paste recommended, the allowed or not allowed reflow temperatures, and the allowed levels of solder joint voiding.

There is no specific IPC standard for voiding criteria associated with devices like LGAs. In some cases, LGA devices with voiding levels up to of 30 per cent have been reliable to date. However, generally speaking, lower voiding levels of 25 per cent maximum are better and 20 per cent is better yet. Figure 2 shows a solder ball with a 20.41% void, which is acceptable for IPC Class II.

Figure 2: Solder ball with a 20.41% void is acceptable for IPC Class II.

In the absence of void data, design engineers have to rely on their experience, know how, and common sense to assure they can perform their designs with easy-to-find components that aren't at an end-of-life cycle and that are available from multiple sources.

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