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Select the appropriate Zigbee system partitioning

Posted: 20 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:ZigBee? wireless networking? transceivers? processors? partitioning?

In addition, the packet data must be transferred between the transceiver and host processor. ZigBee packets can be up to 127B (1016 bits) so transferring a packet to the host processor and back to the transceiver can take 0.5-4 ms at typical SPI/UART data rates. ZigBee uses AES encryption both at the MAC and network layers and sometimes even at the application layer. Additional UART or SPI data transfers will be required if either the host or the transceiver do not support efficient AES encryption.

Figure 2 shows the impact of system partitioning on network performance for a small 5B payload where AES encryption is only supported in the ZigBee transceiver. The latency of a single hop is 10 ms in a network that uses an SoC or NCP and 20 ms in a network that uses a transceiver.

Figure 2: Latency versus system partitioning.

Since it takes each node twice as long to process a packet, the throughput of the network using transceivers has been reduced by 50 per cent, which reduces the maximum number of devices that can be supported at a given activity level by 50 per cent. For timing-sensitive applications such as lighting, the increased latency will limit the maximum number of hops allowed, reducing the scalability and reliability of the network.

Power consumption
The ZigBee communications protocol was designed to allow sleeping end devices to be in control of their battery life. Sleeping end devices set their own schedule for waking and interacting with the network to allow designers to determine the proper balance between battery life and data updates. In addition, the ZigBee protocol does not require any resynchronisation of the sleeping end device when it wakes so the data transfer to its parent is very efficient.

In a ZigBee network, the key power consumption metric is the battery life of the end nodes. A battery-powered end node is typically asleep and only wakes periodically to check if there is any data available from the network. When the battery-powered end device is asleep, the current consumption is dominated by leakage current.

During a data poll, the battery-powered end device must wake the processor, enable the transceiver, perform a clear channel assessment, transmit the data request, receive the acknowledgement and potentially receive data from the network. Most of these functions are performed at the MAC layer without interaction with the network stack. If the network has data for the end node, the time required to send the data from the router to the end node is a function of the system partitioning.

If the router is an SoC or NCP, the data request can be processed internally, and the router typically responds within 2-3 ms. If the router uses a transceiver, the transceiver must wake or interrupt the host processor, wait for the processor to create the data packet and receive the data packet over the serial port, which can add up to 10 ms of delay. During this delay, the end node receiver must remain active, which can significantly reduce the battery life. This is unfortunate in that the device partition on the router has a negative impact on the battery life of the end device.

Cost impact
The cost of a single-chip wireless SoC solution such as an Ember ZigBee SoC or NCP is typically lower than a two-chip transceiver/host processor solution. The PCB cost is lower because less PCB area is required, there are fewer devices to assemble and less signals to route between devices. The total cost of silicon is lower due to the elimination of redundant features such as AES hardware acceleration that are required at the MAC/PHY and network layers and the elimination of serial ports and pins used to communicate between the transceiver and the host. In systems where there is a large host processor, developers often consider it more cost-effective to add a transceiver to the design. However, in these systems, the impact on latency and throughput must be considered as part of this design choice.

For end devices and routers that do not require a host processor, the single-chip wireless SoC system partitioning approach delivers the best network performance, the lowest power consumption and the lowest overall cost. If a host processor is required by the system, the NCP system partitioning approach delivers the best performance and lowest power with the least impact on the host processor performance.

About the author
Thomas Barber is the Director of Marketing for ZigBee products in Silicon Labs' Embedded Systems group. Previously he was the Senior Marketing Manager for Silicon Labs' Human Interface products. He joined Silicon Labs in 2010 as a Senior Business Development Manager. Prior to Silicon Labs, Mr. Barber held Marketing Director positions at ST-Ericsson and NXP Semiconductors, focusing on RF and base band products for mobile communications. He also has served in marketing manager roles for cellular platforms at Analog Devices. Mr. Barber holds an MBA from Northeastern University, an SM (Master's Degree) in electrical engineering from MIT and a BS in electrical engineering from Michigan Technological University.

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