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Research: Software-managed cache shows promise

Posted: 16 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:cache? multi-core memory? Jigsaw? microprocessor?

A team of researchers at MIT has revealed that software, instead of hardware, can better manage high-speed on-chip memory banks known as 'caches.' In order to meet the demand for steadily increasing computational power, chipmakers have to begin equipping their chips with more and more cores, or processing units. And as cores proliferate, cache management becomes much more difficult.

In today's computers, moving data to and from main memory consumes so much time and energy that microprocessors have their own small, high-speed memory banks, known as "caches," which store frequently used data. Traditionally, managing the caches has required fairly simple algorithms that can be hard-wired into the chips.

Daniel Sanchez, an assistant professor in MIT's Department of Electrical Engineering and Computer Science, believes that it's time to turn cache management over to software. This week, at the International Conference on Parallel Architectures and Compilation Techniques, Sanchez and his student Nathan Beckmann presented a new system, dubbed Jigsaw, that monitors the computations being performed by a multi-core chip and manages cache memory accordingly.

In experiments simulating the execution of hundreds of applications on 16- and 64-core chips, Sanchez and Beckmann found that Jigsaw could speed up execution by an average of 18 per centwith more than twofold improvements in some caseswhile actually reducing energy consumption by as much as 72 per cent. And Sanchez believes that the performance improvements offered by Jigsaw should only increase as the number of cores does.

In most multi-core chips, each core has several small, private caches. But there's also what's known as a last-level cache, which is shared by all the cores. "That cache is on the order of 40 to 60 per cent of the chip," Sanchez said. "It is a significant fraction of the area because it's so crucial to performance. If we didn't have that cache, some applications would be an order of magnitude slower."

Physically, the last-level cache is broken into separate memory banks and distributed across the chip; for any given core, accessing the nearest bank takes less time and consumes less energy than accessing those farther away. But because the last-level cache is shared by all the cores, most chips assign data to the banks randomly.

Jigsaw, by contrast, monitors which cores are accessing which data most frequently and, on the fly, calculates the most efficient assignment of data to cache banks. For instance, data being used exclusively by a single core is stored near that core, whereas data that all the cores are accessing with equal frequency is stored near the centre of the chip, minimising the average distance it has to travel.

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