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Configure CoreNet Platform Cache as SRAM

Posted: 25 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:CoreNet Platform Cache? CPC? SRAM? DRAM? Linux?

In this document, we tackle the software methods to configure the CoreNet Platform Cache (CPC) as SRAM for use by Linux applications.

The CPC is a CoreNet-compliant target device that can serve as a general purpose write-back, an I/O stash, a memorymapped SRAM device, or any combination of these functions. As a general purpose cache, the CPC manages allocations and victimisations to reduce read latency and increase bandwidth for accesses to backing store (DRAM). As an I/O stash, the CPC can accept and allocate writes from an I/O device in order to reduce latency and improve bandwidth for multiple read operations to the same address. As an SRAM device, the CPC acts as a low-latency, high-bandwidth memory that occupies a programmable address range.

View the PDF document for more information.

Originally published by Freescale Semiconductor Inc. at www.freescale.com as "Configuring CoreNet Platform Cache (CPC) as SRAM".





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