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Design Linux-based femtocell base-station (Part 2)

Posted: 26 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:embedded systems? Femtocells? IP? software performance engineering? Linux?

Historically, embedded systems implement separate specifications for hardware and software. Hardware partitioning and definition of offload components is done based on mostly inaccurate inputs, on a timeline that is different from that associated with the software design. Hardware specifications need to be available a priori to the silicon design, whereas software work is only started after device (or simulator) availability. Such timelines prohibit extensive re-design of hardware based on software findings, often leading to sub-optimal overall system design and time-to-market.

In the case of a tightly constrained system (due to cost and power consumption) such as the Linux fast-path femtocell design described in Part 1 in this series, concurrent hardware/software design is obviously preferred, and such a system is made possible by the well-defined nature of the end system, a WCDMA/LTE base station operation with known properties. A tailored Software Performance Engineering (SPE) process was used for the performance evaluation activity. In this process, performance calculators are used to model the important performance use cases for the application.

Modelling is a significant aspect of SPE. Some of the performance modelling best practices include using performance scenarios to evaluate software architecture and design alternatives before beginning the software coding and implementation phase. SPE starts with the development and analysis of the simplest model that identifies problems with the system architecture, design, or implementation plans. Details are added as more and more details of the software become apparent.

In the case of the design described in Part 1, as a first step the use case is broken down by its key components for the case of LTE (figure 1), based on the associated protocol stacks that are being implemented (integrated eNB):

Figure 1: LTE components and associated protocol stacks.

In this example, from analysis of the protocol stack the following key performance impacting components were defined:
???RLC/MAC
???Scheduler
???PDCP/GTP
???Transport (UDP, IP, IPSec, QoS, Ethernet)
???RRC/Control plane
???Miscellaneous (e.g. OS overhead)

Pre-silicon modelling targets two goals:
???Definition of SoC architecture with regard to hardware sizing, for example core, cache, bus frequencies, DDR controller configuration, etc.
???Definition of per-component cycle counts that allow for budgeting of resources to software blocks

SoC level modelling
SoC level modelling focuses on architecture exploration modelling of the L1 and L2 domains of the SoC. From a L2/transport perspective, the modelling focuses on the e500v2 Core Complex, Frontside L2 Cache, the coherency manager, DDR queue and controller. Specifically, how DDR traffic from other initiators affects, and is affected by, DDR traffic from the e500v2 Core Complex.

The other DDR traffic initiators modelled were the DSP core, Maple B2F L1 accelerator complex, antenna interface (i.e. Layer 1 processing modules), veTSEC Ethernet controller, and SEC engine. Modelling was performed using a Freescale proprietary System C-based simulation environment.

DDR traffic for the simulations was generated using statistical inputs to generic configurable modules from the modelling environment. Statistical inputs were provided by packet flow analysis based on the use case (amount of traffic to/from the security engine can be derived from over-the-air traffic rates), as well as inputs derived from prototyped software (L1/L2 cache hit rates). The e500v2 Core Complex was modelled in more detail in that its L1 instruction and data caches were modelled. A statistical cache miss rate was also used in the front-side L2 Cache model to determine cache hits/misses.

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