Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

TSMC unveils 16nm FinFET design flows, uses Cortex-A15 core

Posted: 20 Sep 2013 ?? ?Print Version ?Bookmark and Share

Keywords:TSMC? design flows? FinFET? 3D-IC? silicon?

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) recently announced the existence of three reference design flows for FinFET and 3D-stacked ICs that have been taken to silicon. The silicon validation of these flows signifies the opening up of the manufacturing processes for the design of production volume chips.

Intel was the pioneer of the FinFET in commercial production and remains the only company with such a manufacturing process. However, TSMC is reported to have signed to supply Apple with processors on a three-year contract that will include some FinFET.

The three TSMC design flows are: a digital design flow for TSMC's 16FinFET process; a custom design flow for 16FinFET that offers transistor-level design of analogue, digital, mixed-signal, custom digital and memory; and a 3D-IC flow for the design of vertically stacked structures and multi-die assemblies.

EDA software vendors collaborated with TSMC to develop and validate these design routes using silicon test vehicles, said TSMC. However, TSMC did not indicate which companies' tools had been proved effective at which stages of the design process.

The 16FinFET digital design flow uses the Cortex-A15 multi-core processor, licensed from ARM Holdings plc, as its validation vehicle for certification. It helps designers adopt the FinFET by addressing such issues as RC modelling, power-performance-area trade-offs, low-vdd operation, electromigration, and power management.

Integrating multiple components in a single stacked component can provide benefits in terms of physical scaling and power consumption. TSMC's 3D-IC design flow addresses such items as through-transistor-stacking (TTS) technology; through silicon vias (TSVs) plus microbumps, back-side metal routing; and TSV-to-TSV coupling extraction.

"These reference flows give designers immediate access to TSMC's 16FinFET technology and pave the way to 3D-IC Through-Transistor-Stacking (TTS) technology," said Cliff Hou, vice president of R&D at TSMC.

- Peter Clarke
??EE Times

Article Comments - TSMC unveils 16nm FinFET design flow...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top