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Structural, reset faults in SoC designs (Part 1)

Posted: 16 Oct 2013 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? reset? metastability? SoC? metastable?

However, if the assertion of global reset caused by the assertion of any one of the reset sources is completely asynchronous but the reset generation source logic is cleared by global reset, it is likely that there is a combinatorial loop in the design path which can produce a glitch at that reset source. The propagation delay of this combinatorial path will vary with different processes, voltages, or temperatures, causing variations in the glitch width. If combinatorial cells are used for reset assertion and de-assertion then it will also cause race conditions in simulation.

When the reset source SW_Q asserts it will cause the assertion of rst_b which is the global reset (figure 2). If the global reset itself is used to clear the assertion of SW_Q reset, then it will produce glitches in design at the SW_Q output and the global reset. Also, in simulation this will cause a race condition because the assertion of reset source is trying to de-assert itself through this combinatorial logic.

Figure 2: Glitch at reset source (basic problem).

However, if the reset source (SW_Q) is used asynchronously in reset state machine (SET/CLR input of flop) for global reset assertion, then the reset glitch might be able to reset the whole system by asserting global reset. This is because the global system reset de-assertion is not dependent on reset source de-assertion alone.

As a result, there can still be an issue when this reset source (with glitch) is used synchronously or at the D input of a flop. As the glitch width may not be stable at least for a cycle, this will not be captured by the destination flop. Also, this reset source can't be used as clock (pulse capture circuit) of any circuit, as it may cause clock width violations.

Figure 3 shows what happens when there is a glitch at the reset source SW_Q. Although there will not be any glitch at global reset output (rst_b), if the glitch at reset source SW_Q is captured in some flop as a reset status event (at S) or for some other purpose, it will cause a timing violation/metastability condition or it might not get captured at all.

Solution: Other than avoiding situations such as that shown in figure 2, If the reset implementation is configured the way shown in figure 3 then the designer should make sure the reset source (SW_Q in this case) is always used at SET/CLR input of a flop and not at D or CLK.

The best way to resolve this issue is to register the reset source before using it in the reset state machine (figure 4). Although this will cause a clock dependency on global reset assertion, the trade-off is that the assertion of the internal reset(SW_Q) will not also assert when the clock is not present.

Figure 3: Glitch at reset source (problem 2).

Figure 4: Registering the reset source.

Figure 5: Stretch the de-assertion of SW_Q.

Also, the designer can stretch the de-assertion of SW_Q before using it in design which will make the reset assertion independent of clock (figure 5).

About the author
Arjun Pal Chowdhury is Lead Design Engineer at Freescale Semiconductor. He has been working with Freescale and has seven years of experience in SoC Design and Architecture and is involved in designing chips which goes into Automotive as well as Industrial and Multimedia Market.

Neha Agarwal is Senior Design Engineer at Freescale Semiconductor. She has been working with Freescale from last three years in SoC Design and Architecture and is involved in designing chips which goes into Automotive Market. Graduated from Birla Institute of Technology, Mesra in year 2009.

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