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TU Delft, Imec co-author test flow for 3D IC optimisation

Posted: 11 Oct 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Delft University of Technology? Imec? test flow? 3D?

The Delft University of Technology and Imec recently co-developed a new test flow cost modelling tool for 2.5 and 3D stacked integrated circuits. 3D-COSTAR aims to optimise the test flow of 3D stacked ICs by compiling the yields and costs of design, manufacturing packaging and logistics.

"3D-COSTAR has proven to be a crucial tool to analyse the many complex trade-offs in 3D test flows, in terms of both cost and DPPM," said Erik Jan Marinissen, Principal Scientist at Imec. "Among others, we have used 3D-COSTAR to determine when pre-bond testing of the interposer in 2.5D-SICs pays off and what its maximum-allowed test cost can be. In some cases, the overall stack cost reduction amounts to 40 per cent, showcasing that upstream testing can help avoid downstream costs. The tool also demonstrated under which circumstances mid-bond testing (on partially-completed stacks) can be avoided without compromising a high stack yield."

Due to its many high-precision steps, semiconductor manufacturing is defect-prone. Consequently, every IC needs to undergo electrical tests to weed out defective parts and guarantee outgoing product quality to the customer. For TSV-based 2.5D- and 3D-SICs that typically contain complex die designs in advanced technology nodes, testing is even more critical. In addition, there are many possible test moment in their manufacturing flow: pre-bond (before stacking), mid-bond (on a partial stack), post-bond (on a completed stack), and final testing (on a packaged device). Although testing is expensive, filtering out the bad components in an early stage is critical to save costs later on in the production process.

3D-COSTAR uses input parameters that cover the entire 2.5D-/3D-SIC production flow: 1) design; 2) manufacturing; 3) test; 4) packaging; and 5) logistics. It is aware of the stack build-up (2.5D versus 3D, multiple towers; face-to-face or face-to-back) and stacking process (die-to-die, die-to-wafer, or wafer-to-wafer). The tool produces three key analysis parameters: 1) product quality, expressed as defect level (test escape rate) in DPPM (defective parts per million); 2) overall stack cost; and 3) breakdown per cost type.

- Julien Happich
??EE Times





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