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Synopsys, TSMC team up to offer 16nm design solution

Posted: 17 Oct 2013 ?? ?Print Version ?Bookmark and Share

Keywords:FinFET? circuit simulation? design?

Synopsys Inc. has partnered with TSMC to deliver support for voltage-dependent design rules in TSMC's 16nm Custom Design Reference Flow. As part of TSMC's custom design infrastructure, TSMC certified Synopsys' Laker custom design solution and circuit simulation tools that offer capabilities for TSMC V0.5 16nm FinFET process layout design rules, device models, and electromigration and IR-drop (EM/IR) analysis.

"TSMC works with Synopsys to ensure our customers have access to analogue and mixed-signal design tools for TSMC's 16nm FinFET process," said Suk Lee, senior director of design infrastructure marketing at TSMC. "The Custom Design Reference Flow is another milestone of the long term collaboration between the two companies."

"Synopsys continues to build on our strengths in custom design," said Bijan Kiani, VP of product marketing at Synopsys. "Designers rely on us to provide circuit simulation and RC extraction, and are increasingly looking to us as their complete custom design solution provider, particularly with the move to 16nm process technologies."

For the TSMC Custom Design Reference Flow, Synopsys' HSPICE circuit simulation, Laker custom layout and IC Validator physical implementation tools have been brought together to provide a comprehensive solution for voltage-dependent design rule checking. VDRC rules require larger spacing between signals that have a high potential voltage difference. For VDRC validation, voltage ranges are calculated for each net by HSPICE circuit simulation, annotated onto the layout by the Laker layout editor, and then verified using IC Validator signoff verification.

Laker enhancements for 16nm layout include an extensive set of new features for FinFET devices, including fin grid pattern snapping, fin display and interactive FinFET rule checking. Laker's built-in double-pattern checking has been enhanced to support pre-colouring and colour density checking. Laker support for middle end-of-line (MEOL) layers includes contactless connectivity, unidirectional layer rules and enhancements to support 16nm guard rings.

Synopsys has optimised the FinFET model used in HSPICE, CustomSim and FineSim for better performance, reduced memory footprint and enhanced multi-threading scalability. The TSMC Modelling Interface (TMI2.0) jointly developed by TSMC and Synopsys enables more accurate layout-dependent effect modelling on top of standard SPICE models.

TMI2.0 also provides a unified infrastructure for statistical modelling, and MOS ageing simulation.

Synopsys has worked with TSMC to provide full signoff-accurate runsets for design rule checking (DRC) and layout-vs.-schematic (LVS) checks with TSMC 16nm V0.5. IC Validator is also integrated into the Laker user environment to allow running DRC and LVS signoff checks and for debugging layout errors with IC Validator's VUE utility.

Low power design techniques in 16nm designs require accurate, simulation-based EM/IR analyses. Through close collaboration with TMSC, Synopsys has enhanced its CustomSim EM/IR analysis capability to comply with the new rules for 16nm designs and support TSMC's iRCX format, the company stated.

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