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Power mgmt architecture with internal regulation

Posted: 25 Oct 2013 ?? ?Print Version ?Bookmark and Share

Keywords:SoCs? regulator? Bandgap References? Process-Voltage-Temperature? power-up?

Modern day SoCs are designed to support various functions in the field. This requires the SoC to have different IPs, peripherals etc. These sub-systems in the design work on different voltage levels and are power hungry, also having different current requirements. Amongst these voltages, some are externally supplied, while others are internally generated.

For the internally generated voltages these SoCs may have more than one regulator catering to different needs e.g. high bandwidth, low drive and low bandwidth, high drive, but all regulating a single voltage supply (let this be the voltage for the digital IPs). When many of these digital functionalities get activated at the same time there are chances of current surges being seen on this internally regulated voltage supply. As stand-alone entities most of these regulators are flawless but when integrated into the SoC it is particularly important to see that this happens seamlessly.

Some critical issues that should be taken care of during integration are as follows:

a) The enabling of regulators from the Digital wrappers during the power-up phase of the SoC depending on the use case of regulators and its features.

b) The individual regulation levels of the regulators which ensure that the usage of the regulators is optimum and the system is immune to any dynamic current consumption profile changes.

c) Handling the disable of regulators to avoid spikes on the current profile of supply during shut down of the device.

d) Regulators should support bypass feature for Test mode where an external control on all the supplies is needed.

Let us take up each of these issues in detail.

Power-up phase
Masking of data coming from the digital domain: Consider the case when these regulators generate the supply on which the digital logic in the SoC works. Since this supply is building up in the power-up phase of the system, any signal coming from the digital domain is at a floating value, which can be at any level.

Hence this value has to be rejected until at least the digital supply in the system reaches a level after which the digital logic can be trusted. This level, of which the inputs coming from the digital domain should be masked, is the POR_REGULATED_SUPPLY which is about 0.7V (i.e. close to the threshold level of active devices).

???Any logic which the system needs until this level is attained has to be safe-stated to ground level.
???This safe-stating is removed only when the POR_REGULATED_SUPPLY is reached.
???If this is not taken care of, then the system can be stuck in a loop where it will never come out of the Reset state.
Digital wrapper of the regulators: The one problem that often arises in multi-regulated systems is related to the reuse of the logic, residing in the digital wrapper, for power down of the regulators. In general this skips the attention of most chip design and integration verification engineers that though the design of these regulators, namely the MAIN and AUXILIARY regulator, is similar but the functions that they serve in the SoC are different.

How and when these regulators come out of their power down state with respect to each other is very important.

As the work of the MAIN regulator is to build up the internally regulated voltage and to carry the complete load of the device, it should always be ON (i.e. it should start as soon as the POR of the PMU_HV_SUPPLY is released).

The SUPPORTING regulator comes alive when the current load on the MAIN regulator is likely to increase and not by itself bring up the regulated voltage. It will only support the MAIN regulator in regulating the supply during sharp current transients.

Inrush current in regulators: The main regulator should follow a slow ramp to generate the regulated voltage supply. The SUPPORTING regulator does not follow a ramp but a constant voltage value at which it is required to maintain the supply.

There is a reason why the MAIN regulator follows a slow ramp (the ramp rate being the decisive factor) and not a constant voltage or fast transitioning voltage. This is because of following reasons:
???If this not be the case then a huge inrush current (figure 1) will be observed due to the sudden charging of the capacitive loads at the internally regulated voltage node.
???In addition to this, the regulated supply also has to follow the ESD rules, as the ESD trigger circuit sitting inside the supply PADs can issue a false ESD trigger, if the ramp rate of this supply is faster than the ESD specifications.

Figure 1: The ramp rate vs. inrush current in LDO.

Figure 2: Integration of main and auxiliary regulator.

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