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Design the appropriate high-speed ATE hardware

Posted: 04 Nov 2013 ?? ?Print Version ?Bookmark and Share

Keywords:ATE hardware? high-speed? testing? FR-4? DC?

Once the requirements and available information have been identified, we can finally get started with the design.

???What material will be used: FR-4, Nelco, Rogers, etc.?
???Will most of the signals be strip-line, micro-strip, or both? Each has its advantages. If you use micro-strip, take into account the skin effect at high frequencies. If you use nickel plating to plate up and meet the impedance requirements, you will increase attenuation ~3X. It's better to change the FAB notes to only plate lands and use solder resist over bare copper. Solder resist or conformal coat has little effect on attenuation or impedance.
???Depending on the number of lanes, the socket escape, or a requirement to use strip-line, you will have to deal with via structures. ATE load boards are much thicker than system boards 0.062" vs. 0.150" and beyond, so via performance becomes critical. As a rule of thumb, back drill all critical signals or use micro-vias, and use ground return vias to reduce via inductance and signal loss. If possible, use a 50-ohm via structure like the one in figure 1.
???You can also use surface mount through-hole SMP connectors (figure 2) to eliminate vias outside the socket area.
???The socket exit should follow the reference design as much as possible. This may not be possible due to stiffeners, socket keep-outs, etc. Take this into account when choosing a socket.
???Simulating the load board is well worth the time spent for critical signals. This will allow you to tune the vias and remaining structures and exits before going to FAB. You should also get a simulation for the socket vendor if possible. Socket lead times often cause a delay equal to a load board delay and can cause a board redesign. We have also designed test coupon boards to allow both simulation and bench test of the actual vias and structures.
???Remember the bandwidth of the signals is based on the signal rise time and not just the signal data rate. A good rule of thumb is -3dBf = 0.35/tRISE, so a 10ps rise time will equate to a 35GHz bandwidth. Few designs over a few inches in length can meet these requirements.
???Don't forget to match your PN pairs and to account for the maximum lane-to-lane skew.

Figure 2: A surface mount through-hole SMP connector.

Hopefully, this has given you a good starting point in your high-speed load board design and will help you avoid a few critical but easy mistakes that can jeopardise your path to success. Comments and additional clues and tips are always welcome.

About the author
Lance Jones is the VP Technology of Microelectronics Test & Engineering, Evans Analytical Group.

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