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Synopsys reveals DesignWare ARC HS processors

Posted: 08 Nov 2013 ?? ?Print Version ?Bookmark and Share

Keywords:processors? digital TV? set-top box?

Synopsys Inc. has unveiled the 32bit ARC HS34 and HS36 processors as the first products in its DesignWare ARC HS processor family. The processors deliver 1.9DMIPS/MHz at speeds up to 2.2GHz in typical 28nm silicon and are optimised for power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm2) while performing high speed data and signal processing tasks.

The optimisation makes them suited for the embedded and deeply embedded processors within SoCs for products such as solid-state drives, connected appliances, automotive controllers, media players, digital TV, set-top boxes and home networking products, detailed the company.

The ARC HS processor family uses the next-generation ARCv2 instruction-set architecture (ISA), which enables the implementation of high performance embedded and deeply embedded designs with ultra-low power consumption and a very compact silicon footprint. When implemented in typical 28nm processes, the HS cores consume as little as 0.025mW/MHz in an area as small as 0.15mm2. The cores feature a high-speed 10-stage pipeline that supports out-of-order execution, minimising idle processor cycles and maximising instruction throughput. Sophisticated branch prediction and a late-stage ALU improve the efficiency of instruction processing. To speed the execution of math functions, the ARC HS processors give designers the option to implement a hardware integer divider, instructions for 64bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single- or double-precision or both). The ARCv2-based cores provide an 18 per cent improvement in code density compared to previous generation ARC cores, reducing memory requirements. HS processors also support close coupled memory as well as instruction and data cache (HS36 only), with 64bit load-double/store-double and unaligned memory access capabilities that accelerate data transfers. Optional error-correcting code (ECC) hardware is available for all memories in the processor for applications that require a higher level of memory reliability and protection, noted Synopsys.

The highly-configurable ARC HS processors allow designers to tailor each instance of the core on their SoC for the optimum balance of performance, power and area. Users can define instruction extensions to the processor pipeline that enable the integration of their own proprietary hardware accelerators that can dramatically improve application-specific performance while reducing power consumption and the amount of memory required. Native ARM AMBA AXI and AHB standard interfaces are configurable for 32bit or 64bit transactions to optimise system throughput. SoC peripherals can be directly accessed by the CPU in a single cycle, minimising system-level latencies and maximising hardware integration. By incorporating features to optimise the performance efficiency of both the processor and the system, the HS34 and H36 cores give designers the ability to create greater product differentiation while lowering the cost of implementation.

The HS cores are supported by the Synopsys MetaWare Development Kit, a solution for developing, debugging and optimising embedded software on ARC processors. The kit includes an optimised compiler to generate highly efficient code, a debugger for maximum visibility into the software and a fast instruction set simulator (ISS) for pre-hardware software development. A 100 per cent cycle-accurate simulator is also available for design optimisation and verification. Operating system support for the HS processor family includes Synopsys' MQX RTOS, a full-featured real-time OS optimised for deterministic response times and memory size efficiency. Additional third-party hardware and software tools supporting software development on ARC HS processors are available from ARC Access Programme partners include advanced debugging tools from Ashling Microsystems and Lauterbach and ThreadX RTOS from Express Logic.

The DesignWare ARC HS34 and ARC HS36 processor cores and associated development tools are available.





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