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Samsung, SK Hynix set to unveil next-gen memory chips

Posted: 08 Nov 2013 ?? ?Print Version ?Bookmark and Share

Keywords:memory? DDR4 SDRAM? ISSCC?

Samsung is set to demonstrate its low-power DDR4 SDRAMs for smartphones for the first time at ISSCC while SK Hynix roll out its High-Bandwidth Memory, a stack of four memory chips fueling next-gen comms, graphics and server chips. Samsung will describe its 8Gb LPDDR4 chips running at 3.2Gb/s/pin at 1V. The chips support error correction codes and sub-volt operations and are made in a 25nm DRAM process.

The devices mark the highest data-rate and density and lowest supply voltage reported to date, said ISSCC organisers. They are expected to start replacing LPDDR3 chips sometime next year in smartphones and other systems.

In a separate paper, Samsung will describe the smallest SRAM cells reported to date. The 0.064mm2 cell is made in a 14nm FinFET process using novel read/write assist schemes.

For its part, SK Hynix will disclose details for the first time of its High-Bandwidth Memory (HBM). The 8Gb part uses four die stacked using through silicon vias to deliver 128GB/s at 1.2V using a 29nm DRAM process. The device supports eight channels and 1,024 total I/Os.

Samsung, SK Hynix set to unveil next-gen memory chips

Rival Micron has been vocal about its plans for a similar memory stack called Hybrid Memory Cube, aimed at feeding high-end comms, graphics and server processors.

Micron is sampling a 4GB HMC stack delivering 160GB/s. Memory stacks "are expected to create many new applications requiring higher bandwidth in future memory sub-systems," said ISSCC organisers.

Stacks like the HBM hit a new level of throughput. (Source ISSCC)

Separately, Intel will show at ISSCC a Gbit embedded DRAM running at 2GHz at 1.05V and made in its 22nm logic process. A 128Mb macro has a density of 17.5Mbits/mm2 using a cell size of 0.029mm2.

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