Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

RTL signoff: A design imperative

Posted: 03 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:RTL sign-off? SoC? verification? UPF? functional coverage?

By Piyush Sancheti
Vice President, Marketing
Atrenta Inc.

RTL signoff is a must! Why? Simply put, if you are targeting an SoC design that is more than a hundred million gates, includes more than 10 IP blocks, then you can no longer afford to do signoff only at the post-layout stage. You may be risking sleepless nights trying to recover from late stage bug discoveries, delayed tape-out, or a possibility of the dreaded chip re-spin.

"RTL Signoff" as an established concept has gained significance in the last year. However, does a commonly accepted definition of RTL signoff exist? Perhaps not yet, but I am finding common practices among leaders in the industry: RTL signoff is a series of well-defined MUST-pass requirements that your RTL needs to achieve before you commit the design to downstream implementation, i.e. synthesis, layout, etc.

Piyush Sancheti

Sancheti: It is a Herculean task to assure SoC functionality, and device manufacturability, cost effectiveness, battery life longevity and instant-
aneous user response.

Some examples of RTL signoff requirements are: high functional coverage (including high quality assertions), proven-correct clock domain crossings (static and dynamic verification), verified timing constraints (including false and multi-cycle paths), optimal power consumption (and meeting the power budget), verified-correct power intent (UPF), acceptable testability (stuck-at and at-speed coverage) and efficient routability (congestion, area and timing).

To get started you need a complete set of RTL signoff requirements, the means to measure them on your design, and reports to ensure compliance. Some may argue that this is not a new concept, so why now? What has changed? The answer lies in two major trends in the modern SoC design context:

  • Explosion in design complexity resulting from hyper integration of multiple functions on a single chip
  • Increasing reliance on externally sourced semiconductor Intellectual Property (IP) content, both from 3rd party suppliers and from other design groups within the company

In many cases, the SoC replaces an entire printed circuit board (PCB) in a previous generation device, or the entire device itself. That translates into a torrent of functionality (computing, audio, video, wireless, gaming, external interfaces, memory interfaces, power management, etc.), crammed into a single chip the size of your thumbnail. We are beginning to see SoC designs with more than a billion, yes a BILLION gates. It is a Herculean task to ensure all SoC functions work seamlessly, that the device can be manufactured reliably, is cost effective, has hours of battery life, and responds instantly to your every command. While we expect no less from the electronic gadgets we surround ourselves with, meeting all these requirements can become overwhelming.

1???2?Next Page?Last Page

Article Comments - RTL signoff: A design imperative
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top