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RTL signoff: A design imperative

Posted: 03 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:RTL sign-off? SoC? verification? UPF? functional coverage?

This explosion in complexity is further compounded by very short market windows and shrinking product cycles. We are talking windows of 3-6 months sometimes; missing by even a little may transform a healthy profit margin into a significant loss. The need to manage this risk is driving an increased reliance on IP reuse, where a significant portion of the SoC design content comes from sources external to the SoC team. Using proven IP content reduces content design risk, but still leaves risk in assembly and "spec" compliance. IPs are not yet plug-and-play and are open to bugs, misuse and surprises when used outside tested configurations. Any of these problems can derail a project plan that seemed risk-free and on-track.

RTL signoff can address these issues quite effectively, and here's why:

  • I believe it can contribute a 30-50% reduction in design schedule (or, if you prefer, a 30-50% reduction in design schedule risk):

  1. In part because RTL tools run faster than layout tools; you can find and fix a lot more problems at RTL, per unit of time, than you can at layout.
  2. In part, because higher quality RTL reduces risk of iteration from layout back to RTL. Problems caught at layout requiring an RTL change are expensive since they can force a restart of layout design.

  • RTL signoff can be applied very effectively to IP, both internal and external. Since most of IP is sourced as RTL, signoff checks can and must be enforced as part of handoff requirements from the IP supplier, AND as acceptance checks by the SoC team. When dealing with configurable IP, There is no guarantee the configuration you want to use in your SoC has been thoroughly validated by your supplier.
  • A rigorous IP signoff methodology at RTL also enables significant efficiencies for SoC level RTL signoff. At the SoC level you must validate IP assumptions and make necessary corrections when the two are not in sync. Once validated, the SoC level signoff can focus on IP integration and common plane issues at the top level. It should be unnecessary to signoff the internals of IPs at this stage, as long as you can intelligently abstract IP usage models. Abstraction can drive an order of magnitude improvement in analysis time (and hardware requirements) and leads to a greatly simplified signoff flow.
  • In the current competitive climate, RTL signoff is no longer a choice; it is a design imperative. Leading edge SoC design teams have been reaping the benefits of RTL signoff for some years now. It has now made its way into mainstream SoC design flows. If you are not doing it, you should be! Patchwork checklists or ad hoc collection of tools are not a substitute for a disciplined approach. You wouldn't signoff layout with a patchwork of checks, you shouldn't accept anything less than a comparable solution for RTL.


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