Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Xilinx outs comprehensive functional safety design package

Posted: 05 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? safety design package? FPGA? TUV SUD?

Xilinx Inc. has unleashed what it describes as a comprehensive functional safety design package for industrial, automotive, medical, aerospace and defense applications according to IEC 61508 and ISO 26262 safety standards. It includes a TUV SUD certified design methodology and tools that promise to increase design productivity and reduce certification risks.

Xilinx's certified functional safety design methodologies allow system designers to deliver highly differentiated, highly integrated safety compliant solutions with the fastest time to market. The Isolation Design Flow (IDF) and Isolation Verification Tools (IVT) provide a unique and automated methodology to separate system-critical and non-system-critical functions within the same FPGA through physical area isolation, detailed the company.

The independent designs, in isolated locations, can be changed at any time without impacting other isolated locations, which reduces design complexity and development time.





Article Comments - Xilinx outs comprehensive functional...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top