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Latest developments in 3D IC technologies

Posted: 13 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:3D ICs? system-in-package? SiP? wafer? wire-bond?

When we ponder what the world used to be like before the dawn of 3D ICs, we think about the use of lots of small, individually-packaged dice, the advent of system-on-chip (SoC) devices, and the introduction of system-in-package (SiP) assemblies.

In this article, we will consider the various forms of 3D IC technology, starting with the simpler incarnations and culminating in today's start-of-the-art implementations.

Simple stacking technologies
When we start to talk about 3D (three dimensional) ICs, the first thing we have to ask ourselves is, "What exactly do we mean by 3D?" As we shall see, this is not as trivial a question as it may first appear, because "3D" may mean different things to different people. For example, one early form of 3D IC technologywhich is still in use to this day for certain applicationsis to take a group of dice that all perform an identical function (like memory chips, for example), to build them into a 3D stack, to run connecting wires down the sides, and to present the resulting assembly in the form of a system-in-package (SiP).

Figure 1: 3D die stack with connecting wires running down the sides.

Although figure 1 gives the appearance of being tall, thin, and ungainly, it's important to remember that each of the silicon die will be ~0.7mm thick (this may be reduced to only ~0.2mm thick if a back grinding process is used to thin the wafer).

Another approach that is commonly used is to mount one die on the SiP substrate using flip-chip technology, and to then mount a second die on top of the first using wire-bond technology as shown in figure 2.

Figure 2: A simple form of 3D IC/SiP.

Now, both of the technologies discussed above are very clever, but they really aren't what I think of when someone says "3D" in the context of integrated circuits. For that, we have to move to the next level...

Traditional 2D ICs/SiPs
Now, this is where things can start to become a little tricky if we aren't careful, so let's take this part of our discussions step-by-step. In fact, let's begin by taking a step back and reminding ourselves thatin the case of a traditional 2D IC/SiPthe die or dice are mounted in the package in a single plane. The reason I say "dice" is that a traditional 2D implementation may contain multiple chips as shown in figure 3.

Figure 3: A traditional 2D IC/SiP.

For the sake of simplicity, we are showing only two dice in the SiP, butof coursethere could be many more. Also, in this illustration we are assuming that the dice are mounted on the SiP substrate using flip-chip technology (wire-bond technology could also be used). In this case, the flip-chip solder bumps will be ~100?m in diameter.

Let's also assume that the SiP substrate is of the laminate variety. That is, a small, fine-line printed circuit board with copper tracks and copper vias containing a number of tracking layers. Although this form of SiP technology really is incredibly impressive, the tracks on the SiP substrate are orders of magnitude larger than the tracks on the silicon dice. This discrepancy in size impacts performance and power consumption. Also, the larger tracks on the SiP substrate lead to routing congestion that places limitations on the number of die-to-die connections that can be realised.

Active-on-passive 3D ICs/SiPs with TSVs
The next step up the complexity ladder is to place a silicon interposer between the SiP substrate and the dice. As shown in figure 4, the silicon interposer has through-silicon vias (TSVs) connecting the metallisation layers on its upper and lower surfaces.

Figure 4: Active-on-passive 3D IC/SiP using a silicon interposer and TSVs.


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