SoC design success hinges on IP passing JEDEC tests

In this opinion piece, Jonah McLeod of Kilopass Technology asserts that third party IP should pass reliability tests conducted by trade group JEDEC to guarantee longevity in any SoC design.

Reliability testing is an integral part of semiconductor manufacturing, but it is especially critical for suppliers of intellectual property (IP) blocks sold to system on chip (SoC) designers. Major SoC semiconductor manufacturers supply chips into consumer products such as appliances and industrial equipment such as communications switching systems that operate for at least 10 years. When SoC designers purchase an IP block such as a CPU or non-volatile memory (NVM) IP, they must be assured that after the block is incorporated into a larger system, it will pass reliability testing and will last at least a decade in the field.

The Joint Electron Devices Engineering Council (JEDEC) was formed in 1958 as a joint activity between Electronics Industry Association (EIA) and the National Electrical Manufacturers Association (NEMA) to develop standards for semiconductor devices. JEDEC today is best known for setting the standards for DRAM and Flash. However, it also established standards for reliability testing that help assure any semiconductor device that passes testing will operate without failure for at least a decade independent of process, voltage, and temperature.

To test semiconductors and IP in a relatively short period of time, several months instead of years, requires accelerated lifetime tests that use high-voltage and high-temperature stress for 1,000 hours to accelerate and measure failure of potential defects in a device. The accelerated test data is subjected to analysis using statistical models to predict failure rates. The two most common JEDEC tests are high temperature operating life (HTOL) and high temperature storage life (HTSL). HTOL identifies failure mechanisms such as electro-migration, hot carrier effects, Time-Dependent Dielectric Breakdown (TDDB) and charge effects. HTSL shows any parametric shifts in leakage and gain and common failures that occur including bulk die and diffusion defects.

1???2??