Monolithic 3D ICs gain momentum

A recent report on the Solid State Technology website has described how momentum is building for monolithic 3D ICs. Dimensional scaling is clearly not providing transistor cost reduction beyond the 28nm process node, as has been recently confirmed by reports from the large fabless companies such as Qualcomm, Broadcom, Nvidia and AMD. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity.

Consequently, the door has started to open for other kinds of technology that might help to maintain the industry's overall momentum, and monolithic 3D ICs seem well positioned to do so.

As was reported earlier this year, 3D NAND is the first segment of the industry to adopt this new path for scaling. A few months later we learned that BeSang signed a license agreement with SK Hynix for its monolithic 3D technology, which might help Hynix to offer more competitive 3D DRAM. Then we heard that the Singapore-MIT Alliance for Research Technology has ordered EV Group automated production bonding systems for integrating silicon CMOS and compound semiconductor materials to enable new integrated circuits for wireless devices and power electronics. And just last week, CEA Leti announced an agreement with Qualcomm to Evaluate Leti's Non-TSV 3D process.

This explains why Leti's presentation event performed in conjunction with this year's IEDM 2013 features slides promoting monolithic 3D technology as an alternative to dimensional scaling; for example, consider the following slide:

Device technology roadmap (Source: Leti presentation at IEDM 2013)

Leti's presentation goes even further. In the following Leti slide, one can see that monolithic 3D technology is positioned as a far better path to maintain the industry's momentum and offers the cost reduction that dimensional scaling no longer provides. Furthermore, monolithic 3D technology also achieves this with far less costly fab infrastructure and process R&D. As the slide sums it up: "1 node gain without scaling," or as others may say, "The new form of scaling is scaling up."

Interest for M3D. (Source: Leti presentation at IEDM 2013

In monolithic 3D the base stratum might be SOI or bulk, but the upper strata are naturally SOI. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration and Subthreshold Microelectronics. The Subthreshold section fits well, as was presented in this year's plenary talk by Bob Brodersen, who said "The most important technology requirement is to continue the increase in the number of transistors (feature scaling, 3D integration, etc.)."

- Zvi Or-Bach
??EE Times