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Prototyping family optimized for IP, subsystems

Posted: 18 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? FPGA? prototyping? IP? subsystem?

Synopsys Inc. has introduced the HAPS Developer eXpress (HAPS-DX) FPGA-based prototyping system to speed up complex IP and subsystem prototyping. The HAPS-DX system includes customized synthesis and debug software to speed prototype bring-up and streamline the transition from individual IP blocks to full SoC validation. According to the company, it offers up to four million ASIC gates of capacity and is plug-and-play compatible with the HAPS-70 series systems enabling a seamless prototyping solution from IP to full SoC for software development, hardware/software integration and system validation.

The customized prototyping software included with HAPS-DX accelerates prototype availability through automated translation into a HAPS-DX specific implementation. New prototyping diagnostic and fast prototyping modes reduce the RTL review time and provide up to five times faster throughput than traditional FPGA synthesis tools. Time-consuming tasks such as ASIC clock conversion are accelerated using the HAPS clock optimization, allowing even the most complex clocking schemes to be implemented quickly in a clock-limited FPGA architecture. In addition, direct support for Synopsys Design Constraints (SDC) format and Universal Power Format (UPF) speeds the migration of the SoC's timing and power intent into the prototype.

HAPS-DX systems simplify debugging tasks by including the HAPS Deep Trace Debug hardware, in combination with Synopsys Verdi3 debug software. HAPS Deep Trace Debug enables storage of seconds of signal trace data using included DDR3 memory. The flexible debug storage options for HAPS-DX address the need for high-speed sampling and high-capacity storage. In addition, HAPS-DX's debug software seamlessly integrates with Synopsys Verdi3 advanced debug platform to provide enhanced analysis and debug visualization.

Engineers can leverage a broad set of HAPS daughter boards through Synopsys HapsTrak 3 connectors and standard FMCs to minimize the effort of assembling prototypes that connect to real-world interfaces. To speed system validation and software development tasks, Synopsys DesignWare Interface IP such as PCI Express, USB, MIPI and DDR are being pre-validated on HAPS-DX systems enabling software development earlier in the product development cycle and reducing the IP integration effort.

HAPS-DX's integrated UMRBus interface and optional transactors for ARM AMBA interconnect provide a direct connection between a HAPS-DX system and VDKs generated using Synopsys Virtualizer toolset to create an integrated hybrid prototyping environment. Hybrid prototyping enables pre-RTL software development, hardware/software integration and full system validation.

The HAPS-DX FPGA-based prototyping systems are available to early adopters.





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