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The lowdown on high-perf timing in board design

Posted: 23 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:board designer? schematic? clocks? protocols? Time-domain jitter?

It's tough being a board designer (that’s why this author went into management as soon as the opportunity presented itself). Performing all the necessary tasks to generate the full schematic and guide its implementation requires finding the right trade-offs amongst a plethora of competing needs.

The Marketing team is demanding a set of features that will barely fit inside the Vehicle Assembly Building at Cape Kennedy, while the Mechanical Design team has allocated a matchbook-sized cubby hole just behind the corporate logo for your board.

The CTO Office is suggesting some technology they saw in a science-fiction movie last week, while the Purchasing team is insisting you can only use components already on an "Approved Parts List" that is three-quarters vacuum tubes.

The Software team is refusing to consider a new processor since that might require them to port their code. However their request for 8x the RAM of the last design makes you suspect there's a performance problem coming your way when this all hits the lab.

The Power Group has managed to give you an extra 200W of power, but only by giving it to you at 120VAC so that converting it to the needed voltages will count against your thermal budget, not theirs.

And speaking of thermal budgets, you've been asked to make do with 20% less than the last design and the air flow will already be at 75C by the time it gets to your board.

The last thing you need is to scan the datasheet for the PHY chip you've finally got everyone to agree on and see a 3-page table defining its reference clock specifications. A reference clock specification should have frequency and maybe duty cycle. That's all. It better, because your manager only allowed you 2 days before the final schematic review to get the whole clock tree selected and added.

As most board designers are aware, clock component selection is rarely simple any more. The good news is that the leading companies that design and supply timing components have realised the problems their customers are facing and are providing tools to allow the clock tree to be completed quickly by someone without a PhD in analogue design.

Let's take a look at some of the issues that need to be dealt with when selecting and designing-in clocking components today and discuss the assistance available to get each job done.

Within a board design flow, clocking provides a service function to meet the needs of the architectural building blocks. Until those architectural components are chosen, the full list of clock specifications can't be determined. Note that some complex communications systems do address some timing functionality, such as network synchronisation, in the architectural phase. Once the architectural elements are chosen, their power, area and airflow requirements are taken care of by the board designer. Then placement-critical components, such as connectors, faceplate switches and LEDs, etc. are added. This often leaves very little board area, power or cost budget for the service components such as glue logic, power supplies and clocking.

Board area
In all but the simplest cases, there are multiple clocks needed with different protocols, voltages and performance specifications for each. While each needed function in a clock tree can be simply described and is often available as a discrete component, the cost, area and power penalties of using a separate device for each is not viable. For that reason, timing component suppliers have created components that integrate many functions into a single package. This is intended to assist in achieving an optimal board design, but creates the problem of which set of parts contains the optimal mix of functions for your particular requirements. Also, the trade-off priority between cost, area, power and performance can differ from one design to another.

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