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Utilise PSoC for heart rate monitor

Posted: 26 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:heart rate monitor? programmable system-on-chip? IR LED? photodetector? PSoC?

From the earlier description, we see that we need:
???Heart rate sensor (IR diode and photo-transistor pair)
???Three external op-amps: two in the filtering and amplifying stage, and one as a comparator
???One MCU to count the heartbeat rate, calculate the calories burned, and control the display unit. If the MCU cannot directly drive the LCD, an external chip will be required
???One LCD to display the heart rate and the calories burned.

To reduce component count, a single low-cost programmable system on chip such as the PSoC 4 from Cypress can replace the op-amps needed in this application as well as the MCU and LCD interface. Featuring the low-power ARM Cortex-M0 core, combined with programmable mixed-signal hardware, this chip provides a flexible and scalable low-power mixed-signal architecture capable of meeting the analogue I/O, signal processing, and real-time computational requirements of this type of application.

Figure 4 shows how a heart rate monitor of both types can be implemented. For the two-stage amplifier and filter, dedicated op-amps are available. Since the input voltage range is limited to 0 to Vdda (Analogue supply; say 5V), the negative voltage input gets clipped, and only the positive waveform goes through the amplification and filtering stage. The output of the phototransistor is passed through a HPF (High Pass Filter) with a cut-off of 0.7Hz to remove DC fluctuation. The output voltage of the analogue signal conditioning blocks would be of the range 0 to 1.75V (35?V x 50,000 gain = 1.75V).

Figure 4: Circuit diagram of a heart rate monitor (screenshot from PSoC Creator).

The output of the amplifier stage has to be fed to a comparator to generate a train of square wave signals whose frequency is proportional to the heartbeat rate. Dedicated comparator blocks perform this operation. A highly accurate 1.024V reference is used for the Analogue to Digital Converter (ADC). This same voltage source can be fed to the negative terminal of the comparator block.

The pulses coming out of the comparator block can be fed into a counter block (dedicated TCPWM block in PSoC 4) to count the number of pulses occurring per minute. Once the heartbeat is calculated, the internal ARM Cortex M0 core can be used to compute the calories burned. The system can flexibly display the heart rate as well as the calories burned through a dedicated segment LCD block which can operate in either "Digital Correlation mode" or in normal "PWM mode".

Calorie computations involve entering parameters like age and weight. In the past, machines used mechanical buttons that the user pressed to increment/ decrement the age and weight value being displayed on the LCD. Today, most consumers prefer using capacitive sensing touch buttons in the place of mechanical buttons. Capacitive buttons can also be included to start and stop the calorie computation & heart rate monitoring. Capacitive sensing (PSoC CapSense) can supports as many as 35 buttons with high range proximity sensing, water tolerant operation, low power consumption, high scan speed, and high SNR (Signal to Noise ratio).

Power is also a critical design consideration for heart rate monitors. The programmable system on chip must provide low power feasibility and put the system to sleep when it is not performing any operations. Useful power mode options include active, sleep, deep sleep, hibernate, and stop modes, to balance responsiveness with power efficiency.

Since a heartbeat occurs at only one to four times per second, we can put the system into sleep once it finishes computing the calories and beat-rate. The comparator's output acts as a wake-up source, and hence, all these computations can be performed once the device wakes up from sleep. When the computation is complete, the device can again be put back to sleep. Segment LCD components in PSoC 4 have the feature of driving the segment LCD even when the device is in sleep/deep-sleep modes. Since this is a battery operated device, utilising low power techniques like these enable OEMs to differentiate their products with long battery life.

About the authors
Asha Ganesan earned her Bachelor's degree in Electronics and Communication at College of Engineering Guindy as a gold medalist. She is currently working as an Applications Engineer at Cypress Semiconductor. She is gaining experience in PSoC 3 and PSoC 5 products and she assists customers with their PSoC 3/5 projects.

AnandaGanesh M S earned his Bachelor's degree in Electronics and Communication at College of Engineering Guindy. He is currently working as an Applications Engineer at Cypress Semiconductor. He is gaining experience in PSoC 1 and CapSense products and is assisting customers with their projects.

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