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Examining JESD204B converter protocol advances

Posted: 30 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:JESD204? analogue-to-digital converters. ADCs? DACs? FPGA? PHY?

The JESD204 standard applies to analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs). It is primarily intended to provide a common interface to FPGAs, but may also be used with ASICs designs.

As the resolution and speed of converters has increased, the demand for a more efficient interface has grown. The JESD204 interface brings this efficiency and offers several advantages over its CMOS and LVDS predecessors in terms of speed and size. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes that make board designs much easier.

The JESD204 standard is also easily scalable so it can be adapted to meet future needs. This has already been exhibited by revisions the standard has undergone. In fact, the JESD204 standard has seen two revisions since its introduction in 2006 and is now at revision B. As the standard has been adopted by an increasing number of converter vendors and users, as well as FPGA manufacturers, it has been refined, and new features have been added that have increased efficiency and ease of implementation.

Figure 1: High-level representation of a JESD204B system.

What is JESD204B?
The original version of JESD204 was released in April 2006. The standard describes a multi-gigabit serial data link between converter(s) and the device(s) to which they are connectedtypically devices such as FPGAs or ASICs. In the first version of JESD204, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver. The lane is the physical interface between M number of converters and the receiver, which consists of a differential pair of interconnect utilising current mode logic (CML) drivers and receivers. The link is the serialised data link that is established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.

Although both the original JESD204 standard and the revised JESD204A standard were higher performance than legacy interfaces, they were still lacking a key element. This missing element was deterministic latency in the serialised data on the link. When dealing with a converter, it is important to know the timing relationship between the sampled signal and its digital representation in order to properly recreate the sampled signal in the analogue domain once the signal has been received (this situation is, of course for an ADC, a similar situation is true for a DAC). This timing relationship is affected by the latency of the converter, which is defined for an ADC as the number of clock cycles between the instant of the sampling edge of the input signal until the time that its digital representation is present at the converter's outputs. Similarly, in a DAC, the latency is defined as the number of clock cycles between the time the digital signal is clocked into the DAC until the analogue output begins changing.

In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the converter and its serialised digital inputs/outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.

In July 2011, the second and current revision of the standard, JESD204B, was released. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the data rates supported were pushed up to 12.5 Gbit/s, broken down into different speed grades of devices. This revision of the standard calls for the transition from using the frame clock as the main clock source to using the device clock as the main clock source. Figure 1 provides a high-level representation of a JESD204B system that highlights the additional capabilities added by the JESD204B revision.

In the previous two versions of the JESD204 standard, there were no provisions defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link re-synchronisation events, the latency should be repeatable and deterministic. One way this is accomplished is by initiating the initial lane alignment sequence in the converter(s) simultaneously across all lanes at a well defined moment in time by using an input signal called SYNC~.

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