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Exploring monolithic 3D IC technologies

Posted: 30 Dec 2013 ?? ?Print Version ?Bookmark and Share

Keywords:3D ICs? graphene? Monolithic? wafer? metallisation?

In my previous article on 3D ICs, we considered the current state of play. Everything we've discussed thus far might fall under the umbrella of conventional technologies. They are simply evolutionary enhancements (and adaptations) of proven and accepted silicon-based materials and techniques. Other materials, if they came into play, could significantly change the 3D IC landscape.

Take graphene, an allotrope of carbon. It has a structure of one-atom-thick planar sheets formed from carbon atoms packed densely in a honeycomb crystal lattice. In addition to being incredibly strong (measurements have shown a breaking strength 200 times higher than steel), this material is an excellent conductor of electricity. It also has fantastic thermal conductivitybetter than even nanotubes and diamond. Suppose we could lay graphene sheets down layer by layer, patterning each layer with the equivalent of transistors and separating adjacent layers with a few atoms of insulating material. The results could be mind boggling.

Figure 1: Graphene is an atomic-scale honeycomb lattice made of carbon atoms.

Of course, graphene won't be used in this way in the near future, unless something completely unexpected happens. Also, we should recognise the billions of dollars that have been invested in the silicon-based infrastructure. Fortunately, there are other options closer to home.

Monolithic 3D ICs
Here's a 30,000-foot description of a relatively new approach that seems very promising: the Monolithic 3D IC technology. All the following numbers are approximations and/or rounded values. They are intended only to provide a sense of scale.

We start with a regular wafer ~700?m (0.7 mm) thick. The active/device layer (the doped region containing the transistors) is ~20 nm thick1/50th of 1?m, which is infinitesimal when compared to the thickness of the wafer as a whole.

We then add the metallisation layers as usual. These layers may have different thicknesses, depending on what we want them to do (signal or power, for example). Between each pair of adjacent metal layers, we will need an isolation layer (silicon dioxide or a low-k dielectric layer). We end with a final layer of silicon dioxide, and we polish the surface of the wafer to be as flat as possible. In fact, the wafer is polished multiple times as the metal/dielectric layer combos are added.

Figure 2: Cross section of a standard wafer with metallisation.

To provide something to visualise (and to round things furiously), let's say that we have eight or nine metal layers. Adding everything together, the stack of metal and insulating layers is ~1?m thick. This is where things start to get very interesting.

This is so ingenious. We take a second wafer that is also ~700?m (0.7 mm) thick. We create its active layer using a high-temperature process combined with the usual suspects (doping agents) to create P-type and N-type silicon. As usual, this active/device layer is ~20 nm thick (1/50th of 1?m).

This is the clever part. We use a lower-temperature process to dope the entire wafer with hydrogen to a very precise depth of ~50 nm. This does not change the characteristics of the P-type and N-type silicon in the active layer per se. However, as we shall see, it does change the character of the silicon as a whole.

Once we've doped the wafer with hydrogen, we put a protective layer of silicon dioxide on top (no metallisation at this stage), leaving us with a wafer that looks something like the following.

Figure 3: Cross section of a second, hydrogen-doped wafer.

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