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Cadence unveils Incisive 13.2 for SoC verification

Posted: 15 Jan 2014 ?? ?Print Version ?Bookmark and Share

Keywords:verification platform? IP? SoC?

Cadence Design Systems has launched the Incisive 13.2 functional verification platform for intellectual property (IP) block-to-chip and system-on-chip (SoC) verification. The platform features two new engines and additional automation features for faster SoC verification.

For IP block-to-chip verification, enhancements include a new Trident engine in the Incisive Formal Verifier and the Incisive Enterprise Verifier, which improves formal analysis performance up to 20 times; constraint engine in the Incisive Enterprise Simulator that speeds UVM and SystemVerilog testbench simulation, and simulation acceleration with the Palladium platform by up to 10 times; SystemVerilog support in Incisive Debug Analyser plus unique UVM debug capabilities and optimised probing in the SimVision debug environment inside Incisive Enterprise Simulator that reduces database size; and IEEE 1647 e unit testing without simulation, reducing debug time for test bench code by 30 per cent

For SoC verification, enhancements include a comprehensive X-Propagation support in the Incisive Enterprise Simulator and the Incisive Enterprise Verifier to speed SoC reset and low-power simulations and support for SystemVerilog IEEE 1800-2012 real number modelling in the Incisive Digital Mixed Signal option for faster mixed-signal simulation.

"Verification is a growing challenge that we have to address with a finite amount of resources," said Chan Lee, vice president of engineering at Ambarella. "We adopted the X-Propagation support during 2013 to speed our reset simulation performance significantly. The additional automation provided by the Incisive verification platform helps us increase our verification productivity."

"Verification engineers are pressed for time and need strong verification performance. Incisive 13.2 delivers this, but also goes beyond raw clocks per second to encompass capabilities from formal apps, debug, and metric aggregation in order to speed verification closure. The combination of automation and integration provides our customers with real gains to ease the challenges of SoC verification," said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence.

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