Imperas adds support for Imagination's MIPS cores

Imperas Software Ltd has added support for models of Imagination Technologies' MIPS processors to QuantumLeap, a parallel simulation performance accelerator. The accelerator allows virtual platform performance of greater than 16 billion instructions per second, the fastest commercial solution available today, boasted the firm.

QuantumLeap leverages Imperas' synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core personal computer (PC) host machines, noted the firm. The Imperas technology, simulation plus processor core models, provides the MIPS ecosystem with the fastest software simulation solution in the industry.

The Imperas Open Virtual Platforms (OVP) models support the latest architectural features of the MIPS Series5 Warrior generation of cores from Imagination. These features include Single Instruction Multiple Data (SIMD) operations with the MIPS SIMD Architecture (MSA) and hardware virtualization, key features of the new MIPS Warrior cores. The high-performance P-class P5600 has been announced, with entry-level M-class cores and mid-range I-class cores to come later this year and broaden the Warrior generation lineup. Imagination and Imperas are collaborating on the development of the OVP processor core models to ensure the highest quality models for the MIPS community. The Imperas simulators support virtual platforms with both homogeneous processor cores, as well as heterogeneous platforms, for example with both the MIPS P5600 and other Imagination IP cores present.

In the server, home entertainment and mobile markets, most SoC devices incorporate multicore embedded processors coupled with hardware accelerators, all executing in parallel. The performance of existing, single-threaded virtual platform simulators does not adequately scale for these SoCs, creating a barrier to efficient virtual platform-based software development, debug and test.

QuantumLeap eliminates this barrier by allocating the simulated cores across all the processors in a host machine. By ensuring the efficient synchronization of these cores, near linear scaling of the simulation across the multiple host processors has been observed, with the impact of inter-core communication kept to a minimum. Furthermore, QuantumLeap provides a transparent use model, with no change required to the software-under-test, the virtual platform models or the development environment, while ensuring fully deterministic simulation execution. The execution performance of this new technology has been measured on average at 15 times faster than the nearest commercial solution using standard benchmarks, running on a standard 3.4GHz quad core host PC.

QuantumLeap allows full access to the Imperas Multi-core Software Development Kit (M*SDK) verification capabilities. The accelerator includes the ToolMorphing and SlipStreamer capabilities, such that the full tool suite operates with minimal impact to performance and no adverse affect on simulated software operation. QuantumLeap operates on platforms that incorporate both Asymmetric Multi-Processing (AMP) and Symmetric Multi-Processing (SMP) schemes. It has been designed to effectively handle the inter-core communication overhead challenges associated with the most complex SMP processor architectures including, for example, devices based on modern Imagination MIPS Warrior P5600 multi-core processors.