Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Tips for cost-effective 3D IC production

Posted: 19 Feb 2014 ?? ?Print Version ?Bookmark and Share

Keywords:3D IC? Through Silicon Vias? TSVs? printed circuit board? PCB?

From a manufacturer's point of view, 3D IC production will only ramp up if the added costs for implementing Through Silicon Vias (TSVs) and all the subsequent processing steps can be largely compensated by the IC performance benefits, or if the process and materials costs are drastically reduced.

One of the big questions at Grenoble's 3D TSV Summit was: how to distribute the cost-of-ownership across the supply chain?

Who should manufacture TSVs?
In non-MEMS ICs, TSVs must shrink too, because going to the next generation node does not necessarily make sense if your TSV keep-out zone takes too much premium silicon. The processes require equipment sets typically seen in wafer fabs, hence TSV integration could be done by the foundries, but also to some extent by OSAT service providers (Outsourced Semiconductor Assembly and Test). Some printed circuit board (PCB) makers are also looking at embedded dies into PCB substrates, in the form of active interposers for 2.5D integration.

Putting aside the current economic climate which could limit TSV ramp up in the near term, Gartner's Mark Stromberg expects the TSV market to faces capital cost issues that will limit the number of companies able to implement this technology. This is due mainly to the additional capital and material costs, together with more process steps. "As we move to the 10nm node, TSV technology will be require for system design", Stromberg said, noting that the cap-ex requirements will reduce competition with only the top Integrated Device Manufacturers (IDMs), foundries and top tier Semiconductor Assembly and Test Services (SATS) able to compete.

Dr. Miekei Ieong, Vice President of TSMC EMEA, presented his company's CoWoS (Chip-on-Wafer-on-Substrate) services relying on through silicon via technology to integrate multiple chips into one single package using a sub-micron scale silicon interposer. The company offers homogeneous CoWoS in production but says it has already demonstrated heterogeneous CoWoS. A 512bit Wide I/O DRAM test chip was operated at 200MHz and even overdriven up to 285MHz with full operations.

"Our 1024bit TSMC CoWoS DRAM was driven to 1GHz, supporting a bandwidth up to 128GB/s", said Ieong, with plans to tape-out daisy-chained 6 top dices high bandwidth memory by the last quarter of this year.

For the purpose of larger CoWoS, TSMC has also demonstrated silicon interposers up to 26x48mm on a substrate size of 60x60mm. The company says it is ready for stacking memory chips on 28nm logic, and it has characterized TSV design rules for customer's test vehicle design and functional verification.

Global Foundries' Michael Thiele, Responsible for Packaging R&D, exposed his company's readiness with TSV-capable lines installed in Malta, New York, with TSV integration characterized for 20nm devices and 14nm under way. The company has a 300mm TSV line installed in Singapore for Si interposer fabrication and is characterizing TSV integration into 28nm devices in Dresden, Germany.

"Before considering a 2.5D product tape-out, customers expect the foundry to come up with system level qualification data from a representative test vehicle", stated Thiele who then unveiled Global Foundries' dual approach, using external test vehicles with shared R&D but also creating its own internal test vehicle.

Hence, the company develops interposers and micro-pillar interconnects both at OSAT partners and in-house. But Thiele stressed that yield loss, late in the supply chain, could stop the adoption of the technology, especially if there is not a clear yield ownership in the supply chain. Cost reduction at key process steps such as TSV drill and fill, temporary wafer bonding and de-bonding, TSV reveal, is another must for 3D ICs to make it to the mass market.

Cutting on materials and process costs
Director for Industry Development at the A-star Institute of Microelectronics (IME), Surya Bhattacharya sees back-end of line (BEOL) and thin wafer handling (including temporary wafer bonding and de-bondingTBDB) as a real cost-issue for 3D IC components. These added processes alone amount to around 50% of the total final component cost, he estimates.

1???2?Next Page?Last Page

Article Comments - Tips for cost-effective 3D IC produc...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top