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CeRAM gains ARM's attention

Posted: 20 Feb 2014 ?? ?Print Version ?Bookmark and Share

Keywords:nonvolatile memory? semiconductor? correlated electron random access memory? CeRAM? metal-to-insulator transition?

Here's an example of a CeRAM reset/set cycle. Starting with the device in its as-born conducting state, the initial part of the green set-state characteristics is marked in blue to indicate a voltage excursion that would represent a typical read access. If the voltage is increased following the green curve, at about 0.8 V, the characteristic makes a rapid transition to a high-resistance insulating state.

In the insulating state (the red curve in figure 1), from the transition voltage (0.8 V) the current can be reduced towards zero and read cycles can be carried out (indicated by the blue overlay between 0 V and 0.2 V in figure 1), or the voltage can be increased along the red part of the characteristic. In that direction, at about 1.6 V, the current starts to show a much greater increase with increasing voltage to a value where a rapid transition back to the conducting state occurs.

To avoid high levels of damaging current, it is necessary to limit the current to a compliance level (icomp). In the metallic state, the rapid fall in resistance causes the voltage across the device to fall to a value determined by icomp and the metallic state resistance. When the SET pulse is terminated, the voltage across the device will drop to zero, and the device will be in its SET state.

It is worth noting that access along the green curve for another reset cycle is possible only after the voltage across the device has returned to zero (to allow the transient electrons in a non-equilibrium situation to relax). In normal operation, this will occur because switching the device between its set and reset states will use pulses. Proponents say this return-to-reset requirement does not impose latency on the minimum SET and RESET time (due to the speed of phase transition).

Figure 2: (a) Plot of CeRAM switching characteristics on log scale. (b) Linear scan of CeRAM I-V characteristics. (Source: Chris McWilliams)

Figure 2 shows actual CeRAM switching characteristic for real devices taken from the recently published thesis of Chris McWilliams at University of Colorado. Figure 2a is a plot of log current as a function of voltage, while figure 2b is a direct plot from the measuring system. The characteristics are symmetrical and identical in the first and third I-V quadrants.

CeRAM structure
In its simplest form, the CeRAM structure (figure 3) consists of a three thin films of Ni(CO)4 doped NiO nickel oxide between two outer metal conductors. The active material is sandwiched between two films of NiO that serve as buffer electrodes. The two buffer films are doped to be very highly conducting and act as matching electrodes, while the central core active film is nickel oxide with a lower level of similar doping.

The barrier layers play a number of important roles. They provide an ohmic contact to the active material and, more importantly, move any Shottky barrier-like effects caused by the outer electrodes and any unwanted surface states away from the active material electrode interface. These surface states would impede that action of the device. In operation, it is the central region that undergoes the reversible MIT between conducting and insulating states and makes it possible to remain in either state as long as required. This ability is the basis of its potential use as a nonvolatile memory.

Figure 3: A simple CeRAM structure. (Source: Ron Neale)

Though "doping" is a colloquial term used to describe the means by which the NiO structure is modified, the concentration levels are higher than those associated with donor or acceptor doping in conventional single-crystal silicon.

CeRAM: a conceptual view
The fine detail of the physics underwriting the CeRAM mechanism is complex. As an aid to understanding, figures 4 and 5 provide a simplified conceptual view of CeRAM operation.

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