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Creating ARM-based Cloud RAN wireless base station

Posted: 27 Feb 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Cellular service? Cloud radio access network? Cloud RAN? base band? MPU?

Data is transferred between PEs through buffers located in the memory bank. Control messages are transferred between PEs through a dedicated control interface that can connect PEs to other PEs.

System architecture
Figure 5 shows a system block diagram of a proposed BBU. Four quad-core Cortex A-57 processors are used with an MPU co-processor. The A-57 processors are connected to the MPU through an ARM interconnect interface and a high-throughput PCIe interface. Samples coming from the discrete RRUs are connected directly to a CPRI interface located in the MPU chip. The number of CPRI streams is dictated by the number of sectors and the number of antennas per sector that the BBU supports. The CoMp interface is a high-throughput interface used to exchange frequency and/or time domain I/Q samples between cooperated sectors.

Figure 5: BBU architecture.

The system performance and capabilities are highly dependent on many system design choices and parameters, including the MPU/CPU task partition scheme, the algorithms for tasks running on the CPU, the complexity of the L1 scheduler, network duplex mode (TDD or FDD), and the number of Rx and Tx antennas. In order to show consistent assessments, this paper assumes that a sector is configured according to table 1.

Table 1: Sector configuration.

CPU/MPU tasks partition
An earlier study has reviewed various partition alternatives, attempting to find the optimal partitioning between GP CPUs and the co-processor [5]. Offloading too many tasks to the co-processor will improve the performance and efficiency of a GP CPU but it will also diminish the flexibility and ease of programming. An additional critical consideration is how to prevent excessive data transfers between the GP CPU and the co-processor. The most efficient alternative, which balances between the above options, is to run the entire data path on the MPU, leaving the processing of the UL CE, the control channels decoding and encoding, and SRS processing to the GP CPU (figures 6 and 7).

Figure 6: CPU/MPU task partition and PE assignment for LTE DL.

Figure 7: CPU/MPU task partition and PE assignment for LTE UL.


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