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Analyse CDC violations in million-gate SoC (Part 1)

Posted: 04 Mar 2014 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? Clock Domain Crossings? CDC? SoC? verification?

With the growing complexity of SoC, multiple and independent clocks and resets are vital in the design. Here, Clock Domain Crossings (CDCs) are a potential source of design errors. Hence, performing thorough CDC checks is an integral part of any SoC verification cycle. However, running structural CDC on a million-gate SoC throws huge number of violations as the tool is looking blindly for structures wherever there is a Clock Domain Crossing. So, it is tedious to remove false violations and dig out actual functional issues (which might be very less as compared to the reported violations). Based on knowledge of clock switching, paths that are static, paths that are never functionally excited, some protocols, etc. a designer can analyse the paths and ignore the noise i.e. false violations.

This article is split into two parts. Part 1 is data path and Part 2 is reset path

Data path analysis
It has been a general observation that tool runtime is always a major issue while running CDC checks on a huge SoC design. One of the best ways to reduce the runtime of the tool is to know your design well, apply appropriate signal constraints to avoid seeing invalid violations altogether. For example, while doing a functional CDC analysis, it is advised to tie all the Design for Test (DFT) and self-test related signals to their functional values. As it is known that a typical CDC tool will define a new domain at every mux output (if the inputs are from separate domains), you can imagine how many paths can be made transparent if we constrain the test muxes in the design! Similarly, for DFT/self-test mode CDC analysis, constrain the signals to their test mode values.

Below, we have discussed typical SoC design scenarios where we can have CDC violations reported by tool. It is described how a designer should analyse these data paths and when he can waive them off.

CDC paths due to isolation signals
Suppose we have two IPs, IP1 and IP2 in two different power domains but with synchronous clocks. We need to have an isolation cell (say, at Clk3asynchronous to both the clocks) at this power domain crossing to isolate the output signals of a power-gated block during transition from one power mode to another.

The CDC tool will show a violating path from Clk3 to Clk2. However, if we are sure that the clocks to IP1 and IP2 will be stopped before the enable is toggled (which would be the usual case) and will be restored only after switching operation is complete, we can waive such violations. However, there may be cases when clock to IP2 can't be gated. Such cases will have to be reviewed by the designer carefully.

Figure 1: CDC violations at isolation signals.

CDC violations at inout PADS
Due to limitations on number of PADS for a chip, we multiplex different input and output signals onto Inout PADS. In the given structure (figure 2), the tool will structurally identify a CDC violating path from flop of IP2 at Clk2 to flop of IP1 which is at Clk1. But this path is never functionally excited, as based on control signals only one path will be activeeither from PAD to IP1, or IP2 to PAD. Hence, these false paths can be waived.

Figure 2: CDC violations at inout PADS.

Reconverging structures
We can have functional issues at convergence of two synchronised paths. Whenever two data signals are combined after being independently synchronised, there is a potential issue as explained. For any synchronised crossing we know that a new value will be correctly captured, without metastability, on one of two successive receiving clock cycles. But there is no way of knowing on which clock cycle it will be captured. The two combining signals can be arbitrated differently and can end up being received into the destination domain on different clock cycles. However, the functionality requires them to be received in same clock cycle. But we can't guarantee it. So we may observe some unexpected behaviour.

Figure 3: Violations at reconverging structures.

In the case above (figure 3), we can have a reconvergence issue at the output of combinational logic (out). We can ensure that the below structure causes no violation only if one or both the paths are static or toggling of both the paths is mutually exclusive.

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