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A detailed look at Micron-Sony's 16Gb ReRAM

Posted: 06 Mar 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Micron? Sony? ReRAM? CbRAM? CuTe?

A paper presented at ISSCC 2014 titled "A 16Gb ReRAM with 200MB/s Write and 1GB/s Read in 27nm Technology" (Richard Fackenthal, Makoto Kitagawa, et al) has revealed the results from a joint Micron-Sony partnership. The 16Gb ReRAM used CuTe as the active memory material where in a CbRAM cell the growth and removal of a copper filament link through an adjacent thin insulator to a lower electrode provides the two nonvolatile (NV) logic states of the memory.

The ReRAM moved away from the conventional CbRAM structure and introduced a novel dual-cell memory structure. A structure where the top electrode, described as a common-source plate (CSP) is shared by a number of sub elements of the array architecture.

The two bottom electrodes, which require bi-direction writer/erase current, are driven by buried word line MOS select transistors. The memory cell size is 6F2.

Dual cell ReRAM structure

The dual cell ReRAM structure.

The headline characteristic for this new 16Gb ReRAM is the claim by its development team that with this device they have resolved the problems with earlier ReRAMs of either high performance with low bit density or low performance with high bit density and combined both high performance and bit density in one chip.

Based on a 27nm lithographic process using a 3-layer Cu interconnect system, the new memory die size is 168mm2.

Key performance characteristics are a read performance of 1GB/s and write of 200MB/s. While details of the supply voltages Vcc at 1.2V and Vpp of 5V with an on-chip charge pump providing the 6.6V required for programming. However, conspicuous by its absence were the details of power dissipation at the reported write/erase performance levels or for that matter the value of the bi-directional write/erase current needed and provided by the buried MOS selector transistors.

16Gb Micron-Sony ReRAM

The basic architecture of the 16Gb Micron-Sony ReRAM.

Each bank is divided into eight strips that are vertical groups of tiles with a common global bit line. A Y strip is divided into 16 tiles plus a redundant tile, with each tile consisting of a matrix of 8,192+256 local bit lines and 2,048 word lines resulting in a tile size of over 16Mb. During the sense program operation eight tiles (one per Y strip) are activated simultaneously, each accessing a sub page for what is described as a total sense currency of 512+16 cells.

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