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The move to 100A at POL and beyond

Posted: 27 Mar 2014 ?? ?Print Version ?Bookmark and Share

Keywords:processor? FPGA? point of load? POL? MOSFET?

Moore's Law has brought us great amounts of computing power through advanced microprocessors and FPGAs. Massive increases in transistor count have made it possible to implement multiple high-speed processors on a single die, each running at speeds up to 3GHz. But these advances in density and performance have increased the number of problems that face engineers working on power delivery for these loads.

To make transistors operate reliably with dimensions an order of magnitude smaller than those employed just a decade ago, processor and FPGA design teams have had to push supply voltages down to 1V or less for the core of the device. Higher voltages would damage the high-speed logic transistors irreparably. As a result, voltages in the 1.8V to 3V range are only used for specialised I/O devices that interface to memory and peripherals.

But the maximum power envelope of server processors and FPGAs is still in the order of tens of watts, and pushing over 100W for the highest-performance products. The result is a current demand that is beginning to exceed the 100A level at the point of load (POL). Using traditional power-conversion architectures, this demand results in the need for larger components able to handle the high stresses involved.

The traditional approach
The changes could be supported in traditional architectures by devoting more space to the POL converters and decoupling capacitors. But in many of these advanced systems, the available PCB space is not increasing but rather reducing. A further issue is that designing reliable power conversion circuitry able to cope with the high current stresses is a specialised task that is not a core competency for the engineering teams designing PCBs for these advanced processors and logic devices. Without experience in this type of specialised design, the resulting power supply circuitry may be far less than optimal. The design of low-voltage, high-current POL power delivery is complicated by the problem that conduction-related losses are proportional to the square of the output current (I2out), with DC resistance within the inductors, as well as the power transistors and the wiring structure, being significant contributors. A further issue lies in switching losses. During switching transitions, the control switch has a switching loss proportional to Iout Ein and the duration of the switching transition.

The speed of the switching transition is partly governed by the gate turn-off speed of the power transistor, which is limited by a parasitic source inductance that is encountered in standard MOSFET packages. Because of this inductance, the MOSFET can continue to conduct current even though the gate voltage has reached 0V, due the presence of a negative back electromotive force (EMF) caused by the parasitic inductance that pulls the source voltage to a negative level with respect to the gate.

Figure 1: Circuit schematic of the SEPIC-fed buck topology, showing the two current paths.

A different approach is needed
Various improvements in device Rds(on), switching characteristics and drive mechanism have pushed the efficiency envelope to a very mature degree such that large improvements through traditional design techniques are difficult to achieve. To deal with low voltages and high currents, a fresh look at the buck converter is needed.

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