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The move to 100A at POL and beyond

Posted: 27 Mar 2014 ?? ?Print Version ?Bookmark and Share

Keywords:processor? FPGA? point of load? POL? MOSFET?

Shifting to a SEPIC-fed buck (SFB) topology, for example, would fundamentally improve power conversion efficiency and transient response, while retaining the simplicity and low cost of the synchronous buck converter. Both conductivity losses (the sum of conduction losses and inductor DCR losses) and switching losses are addressed and to overcome the issue of I2out R losses in the buck converter, multiple energy delivery paths are used to split the load current. This has the result of cutting conduction losses by the square of the current reduction.

Split current paths
One contribution to the lower losses is a reduction of DC resistance through the inductors for the lower duty cycles that result from the use of a split topology together with the lower output voltages that are required from 100A-capable converters.

The multiple current paths that are fundamental to a SEPIC-fed buck topology reduce the voltage stress on components by almost 50 per cent. As a result, the topology can use lower-voltage MOSFETs and capacitors than a standard buck converter design. Because lower-voltage devices tend to exhibit higher conductivity, the topology is able to use MOSFETs with a lower characteristic Rds(on) than equivalent buck-only designs, which further reduces conduction losses. In addition, the combination of a SEPIC and buck section allows input current to be drawn and load current delivered continuously. When the buck section is switched off, the SEPIC converter is active and vice versa.

The efficiency improvements are not just the result of reductions in conduction losses. The SEPIC-buck topology overcomes a number of problems related to the switching losses of standard buck converters, such as the gate turn-off delay. Furthermore, it enables extremely fast turn-off through the use of the topologys inherent a gate-charge extraction mechanism, which also counteracts the back EMF caused by parasitic source inductance. Due to the lower voltage and current stresses on the power switches, their turn-on losses are significantly reduced as well.

Faster switching and smaller passives
The architecture's reduced current levels means the integrating inductors and increased reset voltage brings a fundamentally faster response from the power stage. These improvements become even more compelling at higher switching frequencies, which improves overall power density. Tests that weve run using this topology (branded by CUI as Solus Power Topology) show that even using the same switching devices as those employed by a buck design, the SEPIC-fed buck topology has the potential to reduce the switching losses by more than 90 per cent. As a result, a converter based on this would operate at a higher switching frequency and reap the benefit of using smaller passive components.

The architecture further benefits designs that provide low-voltage outputs from a higher intermediate voltage. So, as the output-to-input voltage step-down ratio, M, moves from 0.100 to 0.250, the topologys losses are better than a conventional buck regulatorby 91 per cent and 88 per cent, respectively. As the ratio increases to 0.660, the efficiency advantage is 70 per cent. As a result, the topology is highly suited to POL applications that call for a wide-conversion-ratio.

Figure 2: A comparison of switching losses between a standard buck converter and the SEPIC-fed buck topology of the Solus architecture.

The pressure to deliver energy efficiency from these high-current, low-voltage systems means that the processors and support logic need to move into lower-power modes frequently. But they need to restore full capability extremely quickly without suffering from voltage deviations. For example, a voltage deviation of just two per cent can lead to a temporary shutdown that means a web search or VoIP connection fails, costing the service provider potential revenue. Transient response coupled with accurate power delivery is vital in these high reliability systems.

But, having a reduced current in the inductors also brings improvements in transient response. By almost halving the current through its integrated inductors, with respect to the load current in each stage, the load current can rise almost twice as quickly as it could with a standard buck converter. Changes in the applied voltage allow the current to ramp down almost four times faster using a SEPIC-fed buck architecture than a buck when the switch is turned off. Therefore, the power stage is inherently faster under both conditions. The improved transient response reduces the number and size of decoupling capacitors required on the PCB, which translates into further savings in board area.

Adding digital control
This topology handles many of todays issue in voltage deviations during a transient load step and provides for stable operation, especially under fast-changing conditions. However, by coupling this topology with an advanced digital power controller you are able to create a digitally controlled power sub-system. Through the use of a digital controller circuit it is possible to implement much more advanced compensation and control functions than are possible with traditional analogue circuit-based designs. Another advantage of digital switching regulators is that optimising the performance of the circuit can be accomplished more easily and automatically.

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