Dealing with impedances on the test bench

The implementation of broadband impedance-controlled systems challenges designers, manufacturers, and quality assurance managers of the central electronic building component: the printed circuit board (PCB). This does not stem from a lack of electromagnetic design knowledge, but from the enormous price pressure in the PCB industry: i.e. adequate radio-frequency (RF) base materials which are quite justified at clock rates in the Gigahertz range from the developers' point of view are hardly ever used. Instead, low-cost FR4-materials, exhibiting inhomogeneous dielectric constants (DC) across the entire base material, are employed. Moreover, the pressing of cores and prepregs to multi-layer PCBs (these being mandatory, e.g., in most sophisticated embedded systems and backplanes) causes geometrical inhomogeneities, adding another source of uncertainty. However, in order to meet specified tolerances, many PCB manufacturers offer inspection of line impedances, which, in turn, requires additional impedance test coupons. These are usually located at the PCB-margins and thus only partially represent the characteristics of the actual interesting transmission lines distributed all over the produced panel. In the worst case, the measured test coupons may be within the specified range, whereas the actual interesting lines are not.

Impedance fluctuations are often not tolerable
In addition to material and production specific variations, design specific ones (e.g. layer changes, too small distances to GND-planes, PCB borders, or other transmission lines) may occur as well, which eventually result in intolerably fluctuating transmission path impedances. In consequence, clock edges degrade and inter-symbol interferences occur which, in turn, cause inacceptable bit error ratios and, finally, performance degradation or even system malfunctions.

Line impedances can be determined with a high degree of precision by means of a time domain reflectometry (TDR). TDR technology has already been used for detecting faults in underground or submarine cables since the 1970s, where faults can simply be interpreted as large impedance variations. Since then, a lot of applications for fields as different as geology and food technology have been addressed.

Figure 1 shows the block diagram for a TDR-based impedance measurement setup. The TDR itself only consists of a voltage step generator and broadband sampler accompanied by a data acquisition unit.

The basic measurement principle is as follows: The generator emits a step signal travelling via adapters, cables and a probe to the device under test (DUT). While interacting over the entire length of the DUT, the signal experiences partial reflections, which travel back to the detector and thus allow the spatial determination of the DUT's wave impedance. Many people know this basic principle from radar applications, which is also the reason, why TDRs are frequently called Cable Radars.

The rise time tr of the step signal determines the spatial resolution and should thus be as short as possible (for Sequid DTDR-65, this is tr 65ps, allowing a spatial resolution of approx. 5mm). The synchronisation between the generator and the sampler (which should feature an analogue input bandwidth of at least 10GHz) is crucial for low-noise operation, i.e. for jitter values of only some picoseconds. Ideally, a "real-thru" sampler is used; hence no external signal dividers or couplers are necessary. This is highly beneficial, since broadband signal dividers are usually built resistively and thus would add insertion loss and noise. Finally, a TDR features a data recording unit, usually implemented by a microprocessor or FPGA.