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CMOS or FinFET: Exploring cost-effective solutions

Posted: 28 Mar 2014 ?? ?Print Version ?Bookmark and Share

Keywords:node? semiconductor? FinFET? CMOS?

Reconciling cost with advanced node adoption has always been the biggest roadblock that halts the semiconductor industry's efforts to scale to smaller dimensions. International Business Strategies Inc. CEO Handel Jones, suggested four options to cut cost per gate and per transistor even while migrating to later nodes.

The semiconductor industry's growth has historically depended on a reduction in cost per transistor with each migration to smaller dimensions, but next-generation chips will not deliver this cost reduction. The impact of this situation is one of the most serious challenges the industry has faced within the last 20-30 years.

Specifically, next-generation 20nm bulk high-K metal gate CMOS and 16/14nm FinFET process will deliver smaller transistors. However, they will also have a higher cost per gate than today's 28nm bulk HKMG CMOS.

IBS initially projected the increase in cost per gate in 2011.

IBS_Cost per gate

The cost problem stems in part from difficulties obtaining high parametric yields and low defect density at the new nodes.

The 20nm node faces difficulty achieving low leakage due to challenges in controlling doping uniformity, line edge roughness, and other physical parameters that are very sensitive to minor variations in manufacturing processes. The need for double patterning at 20nm also adds cost per wafer over 28nm.

The 16/14nm FinFET node uses the same interconnect structure as 20nm, so the chip area is only 8-10 per cent smaller than 20nm. In addition, this node faces yield issues related to stress control, overlay, and factors related to the step coverage and process uniformity of 3D structures.

The cost problems will persist because, as 28nm bulk CMOS matures, wafer depreciation costs will drop 60-70 per cent from the rampup and initial high-volume phase. As a result, the cost per gate for 28nm bulk HKMG CMOS will be much lower than FinFETs even in the fourth quarter of 2017. A similar pattern will occur for 20nm HKMG in 2018 or 2019 when depreciation costs decline.

The data indicates that FinFETs can be used for high-performance or ultra-dense designs but are not cost effective in mainstream semiconductors. Consequently, the industry faces a mismatch between what is being promoted by wafer vendors and what their customers need.

There's no end in sight for this situation. Scaling to 10nm and 7nm nodes will entail additional wafer processing challenges for which the industry is not well prepared.

The semiconductor industry has four main options to reduce cost per gate and cost per transistor as it scales to future nodes.

Adopt new device structures

One option (which I will cover in a future article) is fully depleted silicon-on-insulator (FD SOI). It gives lower cost per gate and lower leakage than bulk CMOS and FinFETs.

Use 450mm wafers

A key challenge with 450mm is determining which technology node is best suited for the transition. One probable scenario is that 450mm will be adopted at the 10nm and 7nm technology nodes. However, it is not appropriate to adopt extreme ultraviolet lithography and 450mm at the same technology node. That fact complicates the issue.

A 450mm wafer fab that can make 40,000 wafers/month at 7nm will cost $12 billion to $14 billion and will need to be ramped into high volume within a short time. Otherwise, depreciation costs can result in large losses. Such a fab will need to make products that can ramp to high volume rapidly.

There are efforts to address these challenges, but only a small number of companies are committed to this effort globally. Indications are that 450mm wafers will be in high-volume production at multiple vendors after 2020.

Strengthen physical design and design-for-manufacturing capabilities

A complex design in 16/14nm FinFET can cost $400 million or more. Spending another $100 million or $200 million to improve parametric yield means only a small number of applications can be addressed, because product revenue must be 10 times design costs. In addition, designs need to be completed in 12 months in order to support fast-moving markets such as smartphones.

Use software programmability based on embedding multiple processor cores

Programmable structures are expected to be increasingly adopted, but embedded FPGA cores have high power consumption and high costs. Software customisation requires a relatively long time for developing and debugging complex tasks. Software development tools need to be enhanced, but the rate of progress is low.

I welcome input from readers, particularly on what they view as alternatives to the cost challenges of FinFETs. In my next article, I'll go into more detail on FD SOI.

- Handel Jones
??[EE Times/CEO
??International Business Strategies Inc.

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