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Taking a closer look at 20nm bulk CMOS

Posted: 08 Apr 2014 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? 20nm? FinFET? FD SOI? STMicroelectronics?

According to industry experts, fully depleted silicon-on-insulator is the best solution for the 28nm and 20nm technology nodes because of its lower cost and leakage, and higher performance than bulk CMOS. The cost of a 100mm2 die in FD SOI at 28nm is three per cent lower than bulk CMOS and 13 per cent at 20nm due to higher parametric yield as well as lower wafer cost. The data also shows that an FD SOI die with comparable complexity to bulk CMOS is 10-12 per cent smaller.

The combination of the smaller die area and higher parametric yield should give an equivalent product a 20 per cent cost advantage at 20nm for FD SOI compared to bulk CMOS. In addition, at 28nm FD SOI has performance that is 15 per cent higher than 20nm bulk CMOS.

FD SOI performance

FD SOI can provide energy efficiency levels that are far superior to bulk CMOS for low Vdd and high Vdd. The power efficiency of bit cells is superior for FD SOI because of the lower leakage, along with better alpha particle immunity.

Despite these factors, Intel decided to adopt 22nm FinFETs rather than bulk CMOS. It also selected 22nm rather than 20nm in order to eliminate the need for double patterning.

Foundry vendors initially planned to migrate to 16/14nm FinFETs rather than 20nm bulk CMOS. But the reality of FinFETs is that the present device structures do not give cost competitive products through 4Q17.

As a result, foundry vendors modified their plans. At TSMC, for example, 20nm bulk CMOS now is projected to represent 10 per cent of total revenues in 2014 ($2.3 billion) and as much as 20 per cent of total revenues in 4Q14 ($1.1 billion).

However, I believe 20nm bulk CMOS will not provide lower cost per gate designs than 28nm, critical for high volume mobile chips. So there is significant uncertainty in the industry regarding the ramp-up rate of 20nm and 16/14nm FinFETs. One possibility is that 28nm wafer volumes will remain high through 2020.

28nm wafer volumes

Shrinking FD SOI to 14nm (called 10nm by STMicroelectronics) also will give large cost advantage against FinFETs. Consequently, FD SOI provides both short-term and long-term cost, power consumption and performance benefits.

One reason given for not embracing FD SOI is lack of support in the supply chain and concerns with being nonstandard. However, Soitec, SunEdison and Shin-Etsu Handotai supply FD SOI wafers. If the industry adopts FD SOI they can expand capacity to address the supply chain challenges.

Other issues include the need to develop new libraries and IP, gain expertise in body biasing design capabilities and ensure the establishment of design flows. Leading EDA vendors say these areas can be addressed. Body biasing design techniques are not difficult to learn.

When the timeline of the semiconductor industry was based on a two-year window for new generations of process technology, taking an alternate path had high risks. But now with the lengthening of the timeline for new generations of technology, and with 28nm and variants having high wafer volumes through 2020, the higher risk is in not making the optimum decision.

Die, wafer costs of FD-SOI and bulk CMOS

Die, wafer costs of FD-SOI and bulk CMOS.

Die and wafer costs of FD SOI vs. bulk CMOS

Estimates of die and wafer costs of FD SOI vs. bulk CMOS. Source: IBS Inc.

- Handel Jones
??EE Times

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