Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Hardened floating point DSP gives FPGAs a boost

Posted: 24 Apr 2014 ?? ?Print Version ?Bookmark and Share

Keywords:IEEE 754? Altera? floating point? DSP block?

Altera Corporation has revealed that it is integrating hardened IEEE 754-compliant, floating point operators into its FPGAs and SoCs. This work represents an achievement of a company at the top of its game, especially since the design flow involved in the implementation was in itself laborious and time-consuming.

The hardened single-precision floating point DSP blocks included in 20nm Arria 10 and 14nm Stratix 10 devices are based on the company's innovative variable precision DSP architecture. Prior DSP design required fixed-point arithmetic, representing a limited range of values and thus subject to inaccuracies.

IEEE 754 floating point diagram

The hardened DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. They perform up to 1.5TFLOPS in Arria 10 devices and up to 10TFLOPS in Stratix 10. The blocks are backwards compatible with existing designs. Engineers can run these blocks in either IEEE 754 single-precision floating-point mode or fixed-point modes in 18bit standard precision and 20bit high-precision.

Altera architech Martin Langhammer said they added a layer of hardened multipliers and adders to the existing DSP blocks in the architecture, and then tweaked the interconnect. This approach facilitates the direct implementation of designs in the DSP blocks from the C output of tools including OPenCL and Simulink without additional logic usage.

Alterra FPGA_DSP blocks

The integration of hardened floating-point DSP blocks in Altera's devices is estimated to reduce development time by up to 12 months. Designers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point. As a result, timing closure and verification times are dramatically cut.

The company also provides multiple tool flows that allow hardware designers, model-based designers and software programmers to easily target the high-performance floating-point DSP blocks in its devices. The DSP Builder Advanced Blockset, for instance, allows designers to go from system definition and simulation to system implementation in a matter of minutes using the industry-standard MathWorks Simulink tools.

For software programmers, Altera pioneered the use of OpenCL for programming FPGAs and today offers a publicly available C-based, high-level design flow that targets FPGAs. The Arria 10 FPGA floating-point DSP blocks combined with a development flow provide software programmers direct translation to hardware which helps reduce development and verification time.

The IEEE 754-compliant hardened blocks are shipping in Arria 10 devices, whereas the corresponding software and design flows will be released in a few more months. Meanwhile, the Stratix 10 devices with the floating point DSP blocks are due in 2015.

The implementation has been independently verified by BTDI for minimal impact on power consumption and utilisation, Langhammer said. The architecture will be published in peer reviewed journals later in the year.

(With inputs from Nick Flaherty and Clive Maxfield)

Article Comments - Hardened floating point DSP gives FP...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top