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Reducing guesswork in ESD tests

Posted: 13 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:ESD compliance? Transmission line pulse? TLP? TVS? EMC?

Passing an ESD compliance test often makes an engineer's day. Your product has jumped one hurdle on the way to market. Management is pleased, and you leave feeling that you've done your job well. But ESD problems can lurk under the surface. You need to understand why a design passes or fails.

One shortcoming of system-level ESD compliance is the test's binary pass/fail nature. In ESD compliance testing, a product's vulnerable stress points and data ports are zapped with ESD strikes per the desired immunity standard. The product passes or fails. A "fail" condition means a data port IC had physical damage that disrupted the system's operation, or the system experienced a software upset/reset during the testing. A "pass" condition typically means there was no observable physical damage or soft reset, and the equipment can still maintain a link, recover, or operate in a certain specified state after the ESD strikes.

Regardless the test result, there are many unknowns. If the product passed ESD compliance, by how much safety margin did it pass? If this margin is thin, is there a danger of latent failure? Could small, incremental ESD damages aggregate to weaken an IC and eventually result in full device failure?

There are even more questions if the product failed ESD compliance. What stress points and/or interfaces failed? Can the failure threshold be quantified? How much protection and/or PCB routing changes are needed to harden the interface and bring the product into compliance? You simply don't know in a pass/fail test.

With the compliance phase as a barrier to time to market, engineers with passing documentation in hand are eager to leave the compliance lab and hand the product to marketing. Yet a short-term outlook is of little value when ESD problems arise again on future designs. System designers and EMC engineers need a more methodical approach to quantify some of the unknowns. Transmission line pulse (TLP) testing is one method that can help quantify ESD failure thresholds.

TLP measurements have long been used in the electronics industry to characterise the ESD immunity and robustness of on-chip/internal protection structures. In recent years, the TLP technique has also been applied to system-level transient protection devices. Today it is quite common for protection device manufacturers to put TLP data in their datasheets to highlight the performance of their system-level ESD clamps. In this context, the TLP test uses high-current, short-duration pulses to generate IV (current vs. voltage) data that characterizes the semiconductor device under test (DUT).

A typical TLP setup consists of a TLP generator that injects discrete 100 ns square-wave current pulses into a DUT. The 100 ns value nicely approximates the duration and stress of the ESD event. For a single TLP square pulse, the output pulse current is measured, and then the reflected voltage from the DUT is measured. The pulse current is stepped up in a determined increment and the measurement is repeated. Successive measurements create the IV curve data.

Figure 1: A transmission line pulse (TLP) IV curve plots current versus voltage.

Measure dynamic resistance
The IV curve of a protection device shows some interesting things about the clamp structure's behaviour. You can see at what voltage the device will begin to exhibit low impedance (i.e., turn-on or trigger voltage). You can also see the protection clamp's damage threshold, which is generally observed as a sharp secondary snapback in the IV curve. This snapback hints at when the protection element begins to sustain damage. Most TLP generators also allow for monitoring the DUT's leakage current.

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