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3D chip-making technique utilises metallisation layers

Posted: 08 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:3D chip? metallisation? active material?

3D chips bring to mind current fabrication techniques including stacking dies connected by through-silicon vias (TSVs), and another one that leaves out TSVs such as the vertical transistor arrays that BeSang Inc. recently licensed to South Korea's SK Hynix. Yet another technique that uses low-temperature materials claims to be the most flexible and economical method of fabricating 3D chips.

Funded by the Semiconductor Research Corporation (SRC) at the University of California at Berkeley, the novel technique fabricates active devices interleaved between the metallisation layers atop a standard CMOS die, thus eliminating the expense of vertically stacked transistors or of stacking dies with TSVs.

"To me the exciting part of this is that it is a monolithic integration, as opposed to the chip stacking techniques that have been used for 3D integration thus far," Bob Havemann, director of Nanomanufacturing Sciences at SRC, told EE Times. "This method offers a lot more flexibility at a much lower cost."

Using active devices between top layers of metallisation puts a useful new tool in the chip designers tool-box.

"This offers a whole new dimension in designbeing able to put active devices between any metallisation layer. Designers are going to go crazy with this stuff. Their dream has been to be able to put active devices just willy nilly at any level they like, to increase functionality and get the performance they want, and now they can do it."

UC Berkeley 3D chip fabrication

Interferometric thin-film transistor printed above a CMOS substrate metallisation layer covered with oxide (blue). Source: SRC

To be sure, the transistors that can be fabricated at temperatures low enough to not disturb the lower CMOS chip layers are limited in performance, but the Berkeley team claims that these low-temperature materials are useable today and will only get better in the future.

"There are a range of oxide materials using tin, indium, zinc, and gallium that engineers have been developing primarily for display applications," Vivek Subramanian, professor of Electrical Engineering and Computer Sciences at UC Berkeley, told us. "But the performance numbers are getting high enough and the deposition temperatures low enough that they are looking very interesting for integrating over CMOS metallisation."

The technique works by first fabricating the CMOS chip and its first layer of metallisation. After that, the designer has the option of adding more active devices between each layer of metallisation, which on modern chips can be as many as 15 layers.

"It turns out you can make reasonably high-performance transistors on top of CMOS metallisation using these materials deposited out of solution using spin-coating and various types of printing techniques," says Subramanian.

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