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3D chip-making technique utilises metallisation layers

Posted: 08 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:3D chip? metallisation? active material?

Still experimental

The techniques for laying down the transistors are still experimental, but range from spin-coating them and using traditional lithographic techniques to pattern them, to directly printing them using ink jet, or other techniques such as gravure and nano-imprint that extends down to the sub?m range.

"First we put down a layer of dielectric atop a metallisation layer, then we put a layer of transistors on top," says Subramanian. "And the really nice thing is that you can put down additional dielectric layers, freely interleaving transistors between each layer of metallisation. To make this work, you need to use materials that are compatible with the back of the line, and can be fabricated at about 400C. It turns out these materials give us good performance at those temperatureswe are able to deposit oxides and nitrides and get good functionality out of them."

To be sure, these interleaved transistors are not as high-performance as the silicon transistors on the CMOS chip below, only about 20 per cent as fast for an equally sized transistor, but when used for special purposes such as driving sensors or accessing memory, Subramanian claims they are more than adequate.

"Next we plan to add sensors atop metallisation layers using transparent conductors to interconnect them, and what's even more interesting is that many of the materials that we are considering for 3D chips are the same materials that others are looking at for Resistive Random Access Memories, potentially allowing us to stack layers of RRAMs atop processors. Our next step is to continue to improve performance of our transistors, in order to offer more design flexibility, and then to integrate them with RRAMs and memory access transistors."

The SRC funding is in its second year of a three-year program, to be followed by a further development under SRC's Semiconductor Technology Advanced Research Network (STARnet) program under which new applications in sensors, memory, displays, packaging, and wearable electronics are expected to be developed

- R. Colin Johnson
??EE Times


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