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Cadence jumps on 28nm FD-SOI train with IP offerings

Posted: 16 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:IP? FD-SOI? USB? design?

Cadence Design Systems quickly reacts to STMicroelectronics and Samsung's just announced 28nm FD-SOI licensing deal by releasing two intellectual property (IP) solutions for third-party designs on the said platform. The EDA firm also announced support for PCI Express 4.0 for faster completion of functional verification of SoC designs.

On the 28nm process node, the Cadence Denali DDR4 IP supports up to 2,667Mb/s performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. The ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, and is an ideal solution for inter-chip USB applications.

ST finds FD-SOI partner in Samsung
The deal signals a possible expansion of the 28nm mode to low-power smartphones and wearables markets.

The Cadence Denali DDR4 IP solution consists of a DDR PHY and controller that have been verified in silicon for interoperability. The solution supports high-performance systems, including several unique features such as per-bit deskew capability and low-jitter phase-locked loops (PLLs). Additionally, its compatibility to DDR3 and DFI 3.1 standards ensures interoperability with other IP and allows for multiple memory types to be used within the same design.

The Cadence HSIC PHY IP is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 HSIC layer for USB 2.0 high-speed device and host applications. The integrated solution made up of the Cadence HSIC PHY interface with ST's HSIC PHY I/O features extremely low power consumption and silicon area.

Cadence also rolled out a verification IP supporting PCI Express 4.0 architecture that enables designers to quickly and thoroughly complete the functional verification for their SoC designs. PCIe 4.0 doubles the transfer speed of its predecessor, delivering 16GT/s. The specification is at the upper limit of data transmission over copper links.

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