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Cypress debuts asynchronous SRAMs with on-chip ECC

Posted: 19 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Cypress Semiconductor? asynchronous SRAM? Error-Correcting Code?

Cypress Semiconductor Corp. has uncloaked a 16Mb Fast Asynchronous SRAM with Error-Correcting Code (ECC). According to the company, the on-chip ECC capability lets the SRAMs provide the highest levels of data reliability, without the need for additional error correction chips, simplifying designs and reducing board space. The devices ensure data reliability in a wide variety of industrial, military, communication, data processing, medical, consumer and automotive applications, Cypress detailed.

Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress's asynchronous SRAMs performs all error correction functions inline, without user intervention, delivering best-in-class Soft Error Rate (SER) performance. The SRAM achieves a 10ns access time and is pin-compatible with current asynchronous SRAMs, enabling customers to boost system reliability while retaining board layout.

Cypress has also introduced a Fast SRAM with PowerSnooze family that combines the 10ns access times of Fast SRAMs with low standby power comparable to that of Cypress's low-power More Battery Life (MoBL) SRAM family. PowerSnooze is an additional power-saving Deep Sleep mode that achieves 12uA (typical) deep-sleep current for a 16Mb SRAM.

The Cypress 16Mb asynchronous SRAMs are offered in industry standard x8, x16 and x32 configurations. The devices operate at multiple voltages (1.8V, 3V and 5V) over -40°C to 85°C (Industrial) and -40°C to 125°C (Automotive-E) temperature ranges.

The 16Mb Fast SRAM and 16Mb Fast SRAM with PowerSnooze are sampling in industrial temperature grade, with production expected in October 2014. These devices will be available in RoHS compliant 48-pin TSOP I, 48-ball VFBGA, 119-ball BGA and 54-pin TSOP II packages.

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