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Cadence PHY IP scales up DDR4 speed up to 3200Mbit/s

Posted: 20 May 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? DDR4? PHY IP? 16nm FinFET?

Cadence Design Systems, Inc. has launched its DDR4 PHY IP, which is built on TSMC's 16nm FinFET process, and specified to scale up to 3200Mbit/s while backwards compatible with earlier DDR3 and DDR4 specifications.

The technology enables server, network switching, storage fabric and other SoCs requiring high-memory bandwidth. It targets the microserver marketlow-power servers that have small demands on compute power but high demands on moving high numbers of data traffic. Other markets include equipment used in enterprise datacenters C servers, network switches, storage fabric, and other SoC designs that require high-memory bandwidth in a leading-edge process.

The IP supports an unbuffered dual in-line memory module/registered dual in-line memory module with reliability, availability, and serviceability features such as cyclic redundancy check and data bus inversion. It implements architectural innovations such as 4x clocking to minimise duty cycle distortion, multi-band power isolation for increased noise immunity, and I/O with slew rate control.





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