PDK delivers power noise, reliability sign-off flow

ANSYS, Inc. and TowerJazz will jointly deliver comprehensive power noise and reliability sign-off flow in a process design kit (PDK) to accurately predict the performance of these ICs prior to production.

The PDK includes reference flow guidelines, collateral, example test cases and flow setup guidance that will enable analogue and RF designers. The designers can utilise Totem and PathFinder, and facilitate the manufacturing of their products in accordance with TowerJazz's process requirements.

Totem is used to validate and sign-off custom macros or IPs against static and dynamic voltage drop. It creates detailed models of the IPs, verifying that these are connected appropriately at the SoC level and that operation at the full-chip level is not adversely affected due to poor design or noise coupling issues.

Figure 1: Totem multi-pane graphical user interface. Source: ANSYS

PathFinder, on the other hand, includes comprehensive layout connectivity and interconnect failure analysis capabilities. It provides extensive design prototyping features for early ESD planning, especially for large, multi-voltage island SoCs using advanced sub20 nm process technology nodes.

Figure 2: Identification of high resistive path using PathFinder. Source: ANSYS

The tools will be useful in cases where voltage drop and specialised reliability checks such as electromigration and ESD simulations cannot be performed using Layout Versus Schematic, Design Rule Check, and extracted simulation tools.