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H.265 decoder core boasts real-time streaming at 150MHz

Posted: 03 Jun 2014 ?? ?Print Version ?Bookmark and Share

Keywords:H.265? video? decoder? CAST?

CAST, Inc. has launched the first in the series of its H.265 video decoder cores, which handle video steams in real time without need for software computations running on a CPU, at the Design Automation Conference.

The H.265-MPI-D achieves real-time performance for full HD resolution (1080p) at a clock frequency of approximately 150MHz.

The core is sourced from the Fraunhofer Heinrich Hertz Institute (HHI). Fraunhofer engineers participated in the standards effort leading to H.265 HEVC. The core fully conforms to the resulting ISO/IEC 23008-2 HEVC and ITU-T H/265 standards. Fraunhofer HHI is also known as one of the few sources for the complete H.265 compliance test streams used throughout the industry, and the core has been rigorously verified using them.

The decoder design leverages the internal and external memory. Its application-specific internal memory architecture enables reuse of already fetched data, which keeps more memory transfers within the chip to yield lower external memory bandwidth and power consumption. The core has a high tolerance to memory latency (delay), which is critical when expensive external memory is shared with other blocks such as a CPU.

The core's performance, coupled with the its full-hardware and CPU-less decoding ability, figures well in applications requiring real-time H.265 performance but having power, packaging, or budgetary constraints.

The decoder core is scheduled for availability in the third quarter of this year.

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