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Chip industry to face hurdles brought by 20nm tech

Posted: 01 Jul 2014 ?? ?Print Version ?Bookmark and Share

Keywords:KLA-Tencor? Applied Materials? NAND flash? DRAM? lithography?

According to executives from two capital equipment companies, the semiconductor road map is becoming as narrow and twisting as a mountain road. They also stated that chip vendors face the challenges brought by higher costs and complexities due to tighter margins, new processes and materials at 20nm and beyond.

In logic, foundries and their fabless customers have yet to settle on a new set of design rules. In memory, NAND flash has started a shift to 3D design other chips are likely to follow in some form, and DRAM faces a major materials shift, probably in 2015.

At 20nm, the overlay budget of about 6nm will shrink to about 4.5nm while specifications for critical dimensions will narrow from 3-2nm, noted Brian Trafas, chief marketing officer at KLA-Tencor. He also predicts a 30 per cent increase in process control spending between 28nm and 20nm nodes to handle the requirements for multiple lithographic patterns needed to define some mask layers.

Chipmakers are using multi-patterning in four to ten mask layers starting at 20nm and the follow-on node. In addition, these nodes are adding on a number of new deposition and etch steps, Trafas said.

Additional mask costs alone could be as much as $3 million for each chip design based on merchant costs of about $150,000 per mask, indicated Chris Bencher, a distinguished member of technical staff in the office of the CTO at Applied Materials. "Between the 45nm and 16nm nodes, chipmakers are going from 50 to 70 masks per device."

Flash chip designers pioneered ways to use multi-patterning while not raising costs to make small, but regularly shaped, features for generally small chip dies. However, logic designs use larger dies and want irregular patterns that help boost performance and lower power, stated Bencher.

As a result, "in logic, there's a battle between the designer and lithographer to find compromises that don't add too many masks and delay the need for double or triple patterning," said Bencher, who is considered Applied's lithography guru. In short, logic chip designers "are in a world of hurt."

"Intel is uniquely positioned because they have the designers and lithographers both in-house and can drive compromises internally. Foundries are more challenged: How do they tell customers they don't want them to put a jog in metal-layer 1?"

Flash designers showed ways to use two masks per active layer, but the techniques require maintaining a common set of critical dimensions across a chip. Logic designers want to vary these dimensions to raise performance and lower power, forcing a need for three masks per critical layer, he said.

Most foundries have yet to start buying the capital equipment needed for the 14/16nm node, which for many will be the first to support FinFETs, stated Trafas. Gear companies hope the orders start coming in the fall.

Meanwhile most fabless designers are testing out the waters in 20nm to get their first taste of the new multi-patterning techniques.

"Some companies have made the transition to 20nm, and others decided to skip it and go to 16/14nm," Trafas stated. "While there is 20nm spending happening, I think 16/14nm, due in part to higher complexity, will be a higher investment level."

SADP evolution through the years

Indeed, he said, one of the big questions many capital equipment execs will bring to this year's Semicon West event on July 7 is, "When will the 16/14nm investments begin?"

Work on that node "is very early, focusing on initial test devices such as SRAMs. A unique issue is at that node the back-end design rules are getting tighter with multi-patterning challenges at metal-1 and above."

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