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Cadence RC extraction tool qualified for 16nm FinFET designs

Posted: 16 Jul 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? FinFET? RC extraction? TSMC?

Cadence Design Systems Inc. has unleashed its next-generation tool for RC extraction that the company said boasts massively parallel architecture. The Quantus QRC Extraction Solution claims to speed design signoff and sets a new standard for performance by delivering up to five times faster runtime for single and multi-corner extraction versus competing solutions. Additionally, its accuracy and FinFET functionality have been certified at TSMC.

Quantus QRC Extraction Solution leverages the high-accuracy modelling engine from Cadence's previous-generation QRC Extraction product, ensuring direct compatibility and fully certified libraries for all foundries for existing users of QRC Extraction. The tool also provides significant enhancements to support FinFET features. It includes the same market-leading custom/analogue functionality of QRC Extraction, and supports the same foundry-certified and -qualified "qrctechfiles." In addition, Quantus QRC Extraction Solution is proven to have the tightest correlation to foundry golden data at TSMC versus competing solutions, Cadence noted.

Quantus QRC Extraction Solution supports both SoC and custom/analogue designs and includes a foundry-certified integrated random-walk field solver called Quantus FS. An automated incremental extraction capability reduces design closure turnaround time with up to an additional 3X performance improvement with Cadence Encounter Digital Implementation System and Tempus Timing Signoff Solution. In-design signoff methodology has been enhanced in both Encounter and Virtuoso platforms.

Quantus QRC Extraction Solution is available.

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