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Fundamentals of resistive memory devices

Posted: 24 Jul 2014 ?? ?Print Version ?Bookmark and Share

Keywords:non-volatile memory? NVM? NAND flash memory? MOSFET transistors? Resistive random-access-memory?

This plausible explanation can bring into question that the speed of current-limit engagement may be important for ReRAM forming and therefore worthy of additional characterisation. In the industry, it still not common knowledge that the speed of a DC (SMU) current limit is relatively slow (in the ~100?sC1ms range).

An ideal solution to this problem is to design structures with current-limiting control transistors directly on-wafer. This will ensure minimum parasitic capacitance and minimum response time. If a current limit is not available on the wafer, using both SMU instrument current limiting and Model 4225-RPM current limiting independently makes it possible to gain a better understanding of forming mechanisms, for example.

After forming, the applied RESET pulse changes the resistance of the structure from low to high. This is thought to be caused by the destruction of the conductive filament in the vicinity of the one of the electrodes. ReRAM structures can be symmetrical or polar. Polar devices require certain polarity of the forming pulse, and have non-symmetric material layouts. For polar devices, the Forming (and SET Pulse) have an opposite polarity from the RESET pulse.

The first test in the ReRAM section of the NVM_Examples project is a standard characterisation test, which verifies that a ReRAM device is valid and can be used. The remaining tests include a Forming and a SET/RESET sequence (usually called the "Butterfly Curve"). The last test is an Endurance test. Figure 3 shows the pulse and SMU instrument connections for a two-terminal ReRAM device.

Figure 3: Test connections for a two-terminal 1R ReRAM device.

In figure 4a, the blue curve, using the left y-axis, shows transient voltage applied to the ReRAM device for initial characterisation (before the forming process). The red curve, using the right y-axis, is the current response. Note that the x-axis is time, in hundreds of microseconds. The voltage amplitude is 2.3V. The same data is also plotted as I vs. V as shown in figure 4b. Exponential dependency of the current on the bias demonstrates that the device is not yet formed and can be used for characterisation.

Figure 4a: Characterisation test of ReRAM structure, showing the transient voltage applied (blue) and the current response (red) vs. time on the x-axis.

Figure 4b: The same data shown in figure 4a, plotted as I vs. V.

This data was collected with one model 4225-PMU ultra-fast I-V module and two model 4225-RPM remote amplifier/switch modules using the reramSweep test routine. This same test routine can also be configured to use SMU instruments to collect similar data. However, these different configurations mean differences in how the tests are performed. First, the SMU instrument sweep takes significant time, up to several seconds. But a sweep performed using the PMU and RPM can be as fast as hundreds of nanoseconds. Second, the current limit capability for an RPM is much faster than an SMU instrument. A SMU current compliance "engage time" is approximately 100C500?s, depending on the particular configuration and SMU instrument model, but an RPM-based current limit can be as fast as several hundred nanoseconds, effectively ~3 orders of magnitude faster. Although a control transistor, located on-wafer, would be faster and better in terms of energy control, the RPM current limit does offer research advantages over SMU instrument testing. Using the PMU+RPM instrument combination provides information that may help during the complicated and potentially costly transition to adding an on-wafer current limit capability.

Another benefit to the pulse approach is using a second PMU/RPM channel to avoid capacitive charging effects by measuring the current through the test device on the low or side opposite the pulsing (figure 5). The faster current limit is also useful during constant voltage stressing (CVS) used for reliability testing. CVS is traditionally performed using SMU instruments, but it can also be done using the PMU+RPM approach.

Figure 5: Two pulse I-V channels connected to a two-terminal device, such as a ReRAM device.

My next article will further address issues related to characterisation and forming, as well as endurance testing for 1R ReRAM structures.

About the author
Peter J. Hulbert is the Product Development Engineer at Keithley Instruments.

To download the PDF version of this article, click here.


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