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Utilising ARM Cortex-M based SoCs (Part 2)

Posted: 28 Jul 2014 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chips? ARM? Cortex M? SoC? PSoC?

Interrupt handling and latency. Interrupts play a key role in embedded system and application development. Interrupts provide information to the system that some event has happened and some decision is required to be taken. Interrupts are very important when the CPU is handling many tasks simultaneously.

Key challenges while handling interrupts are interrupt latency and interrupt priority. Application performance and reliability will be impacted if these key challenges are not handled properly. For example, in the gas sensing system we discussed earlier, the buzzer is driven using a software-based PWM. A timer is generally used to generate a software-based PWM. If there is latency in serving the timer ISR or its interrupt priority is low, the PWM frequency will vary, causing audile jitters in the buzzer sound.

Interrupt latency is the time difference between the arrival of an interrupt and the moment when the first instruction of the corresponding interrupt handler is fetched and executed. Interrupts must be serviced with the least possible delay. Any delay in servicing interrupts can cause embedded system failure. Interrupt latency is reduced in an ARM-based SoC through the use of the Nested Vector Interrupt Controller (NVIC). A vector table and tail chaining help achieve low interrupt latency.

The vector table contains the addresses for all exception handlers, including the reset address. It avoids software overhead and reduces interrupt latency. To reduce latency when another exception is pending, the processor does not restore all saved registers from the stack; rather, it executes the pending interrupt.

Interrupt prioritisation is important in determining the order of execution when two or more interrupts occur simultaneously. Here it's the importance, urgency, and frequency of tasks that decide priority.

Frequently occurring interrupts should be assigned a higher priority so that all interrupt requests are serviced. Otherwise, there is a possibility that multiple interrupt requests result in servicing multiple requests only once. This might occur if the second, third, or a number of interrupts occur before the first request is serviced.

ARM Cortex-M processors provide configurable interrupt priorities and efficient techniques to handle nested interrupts. The number of priority levels varies with between members of the Cortex-M family.

The ARM core must be able to service higher priority interrupts by putting lower priority interrupt execution on hold. This is required in the case of critical interrupts. ARM deploys multiple techniques to handle interrupts efficiently.

Tail Chaining: As discussed above.

Stack pop pre-emption: If another exception occurs during the un-stacking process of an exception, the Cortex-M abandons the operation and services the pending interrupt immediately.

Late arrival: If an interrupt with higher priority comes while stacking of a lower priority interrupt, the Cortex-M stops the process and services the higher priority interrupt first.

Rules of thumb for interrupt handlers:

???Keep interrupt handlers as small as possible.
???Process only the essential tasks in interrupt handlers.
???Limit the overall time spent in interrupt handlers.

Memory footprint
Memory footprint is the measure of main memory used or referenced by a program while it is executing. It is the sum total of program code, data variables, heap, stack, tables, etc. required for the proper working of an application.

Memory requirement is directly proportional to the silicon die size. The greater the demand for memory, the greater is the cost of the silicon. Hence, reducing memory footprint is beneficial as it results in a reduction of overall system costs. ARM-based SoC helps reduce memory footprint by using Thumb-2 instruction technology and efficient compiler optimisations.

Thumb-2 Instruction technology: The Thumb instruction set is an extension to the 32bit ARM architecture that enables greater code density. The Thumb instruction set features a subset of the most commonly used 32bit ARM instructions that have been compressed into 16bit wide operation codes. This results in higher code density and benefits developers by reducing overall memory requirements and enable on-chip flash to be utilised to its maximum capacity.

Efficient compiler support: ARM provides efficient compilers to generate more compact and optimised code.

Other advantages of an SoC-based ARM design
In addition to the above outlined capabilities, the use of the ARM Cortex-M in an SoC design brings with it a range of other advantages including speed of operation, resource sharing, Intellectual Property (IP) protection, and lower power operation.

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